SAA7185B Просмотр технического описания (PDF) - Philips Electronics
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SAA7185B Datasheet PDF : 36 Pages
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Philips Semiconductors
Digital Video Encoders (DENC2-M6)
Preliminary specification
SAA7184; SAA7185B
In the master mode, the time base of the circuit is
continuously free-running. At the RCV1 port, the IC can
output:
• A vertical sync signal (VS) with 3 or 2.5 lines duration, or
• An odd/even signal which is LOW in odd fields, or
• A field sequence signal (FSEQ) which is HIGH in the first
of 4 respectively 8 fields.
The IC can provide a horizontal pulse with programmable
start and stop phase at the RCV2 port. This pulse can be
inhibited in the vertical blanking period to build up, for
example, a composite blanking signal.
The phase of the output pulses at RCV1 or RCV2 are
referenced to the VP port, polarity of both signals is
selectable.
The DENC2-M6 is always the timing master for the source
at the MP input. The IC provides two signals for
synchronizing this source:
1. At the RCM1 port the same signals as at RCV1
(as output) are available.
2. At RCM2 the IC provides a horizontal pulse with
programmable start and stop phase.
The start and end of the active part can be programmed.
The active part of a field always starts at the beginning of
a line if the standard blanking option SBLBN is not set.
Control interface
DENC2-M6 contains two control interfaces, an I2C-bus
slave transceiver and an 8-bit parallel microprocessor
interface. The interfaces cannot be used simultaneously.
The I2C-bus interface is a standard slave transceiver,
supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write only,
except one status byte which can be read.
Two I2C-bus slave addresses can be selected
(pin SEL_MPU must be LOW):
88H: pin 61 = LOW
8CH: pin 61 = HIGH.
The parallel interface is defined by:
D7 to D0 data bus
CS active LOW chip select signal
RW read/write signal, LOW for a write cycle
DTACK 680xx style data acknowledge (handshake),
active-LOW
A0 register select, LOW selects address, HIGH selects
data.
The parallel interface uses two registers, one
auto-incremental containing the current address of a
control register (equals subaddress with I2C-bus control),
and one containing actual data. The currently addressed
register is mapped to the corresponding control register.
The status byte can be read (optionally) via a read access
to the address register, no other read access is provided.
Input levels and formats
DENC2-M6 accepts digital YUV data with levels (digital
codes) in accordance with CCIR 601.
Deviating amplitudes in the colour difference signals can
be compensated for by independent gain control setting,
while the gain for luminance is set to predefined values,
distinguishable for 7.5 IRE set-up or without set-up.
The MPEG port accepts only 8-bit multiplexed CCIR 656
compatible data.
If the I2C-bus interface is used, the VP port can
accommodate both formats, 8-bit multiplexed Cb-Y-Cr
data on the VP lines, or the 16-bit DTV2 format with the Y
signal on the VP lines and the UV signal on the DP port.
Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.
1996 Jul 03
9
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