SAA7114 Просмотр технического описания (PDF) - Philips Electronics

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SAA7114

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI data slicer and high performance scaler

Philips Electronics 

Philips Semiconductors

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb filter, VBI data slicer and high performance scaler

Product specification

SAA7114

PIN

SYMBOL

LQFP100 BGA156

RTCO

36

L13

AMCLK

37

K12

VSSD(ICO1)

38

K11

ASCLK

39

K14

ALRCLK

40

J13

AMXCLK

41

J12

ITRDY

42

J14

VDDD(ICO2)

43

TEST0

44

J11

H13

ICLK

45

H12

IDQ

46

H14

ITRI

47

G14

IGP0

48

F14

IGP1

49

G13

VSSD(EP2)

50

VDDD(EP3)

51

IGPV

52

H11

G11

F13

IGPH

53

G12

IPD7

54

E14

IPD6

55

D14

IPD5

56

C14

IPD4

57

B14

VDDD(ICO3)

58

F11

IPD3

59

E13

IPD2

60

D13

IPD1

61

C13

IPD0

62

B13

TYPE(1)

DESCRIPTION

(I/)O

O

P

O

(I/)O

I

I/pu

P

O

I/O

O

I(/O)

O

O

P

P

O

O

O

O

O

O

P

O

O

O

O

real-time control output; contains information about actual system clock

frequency, field rate, odd/even sequence, decoder status, subcarrier

frequency and phase and PAL sequence (see external document “RTC

Functional Description”, available on request); the RTCO pin is enabled

via I2C-bus bit RTCE; see Table 36 and notes 3 and 4

audio master clock output, up to 50% of crystal clock

internal digital core supply ground 1

audio serial clock output

audio left/right clock output; can be strapped to supply via a 3.3 kΩ

resistor to indicate that the default 24.576 MHz crystal (ALRCLK = 0;

internal pull-down) has been replaced by a 32.110 MHz crystal

(ALRCLK = 1); notes 3 and 5

audio master external clock input

target ready input, image port (with internal pull-up)

internal digital core supply voltage 2 (+3.3 V)

do not connect; reserved for future extensions and for testing: scan

output

clock output signal for image port, or optional asynchronous back-end

clock input

output data qualifier for image port (optional: gated clock output)

image port output control signal, effects all input port pins inclusive

ICLK, enable and active polarity is under software control (bits IPE in

subaddress 87H); output path used for testing: scan output

general purpose output signal 0; image port (controlled by

subaddresses 84H and 85H)

general purpose output signal 1; image port (controlled by

subaddresses 84H and 85H)

external digital pad supply ground 2

external digital pad supply voltage 3 (+3.3 V)

multi purpose vertical reference output signal; image port (controlled by

subaddresses 84H and 85H)

multi purpose horizontal reference output signal; image port (controlled

by subaddresses 84H and 85H)

MSB of image port data output

MSB − 1 of image port data output

MSB − 2 of image port data output

MSB − 3 of image port data output

internal digital core supply voltage 3 (+3.3 V)

MSB − 4 of image port data output

MSB − 5 of image port data output

MSB − 6 of image port data output

LSB of image port data output

2004 Mar 03

8

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