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SAA7114

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI data slicer and high performance scaler

Philips Electronics 

Philips Semiconductors

PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC

comb filter, VBI data slicer and high performance scaler

Product specification

SAA7114

7 PINNING

PIN

SYMBOL

TYPE(1)

LQFP100 BGA156

DESCRIPTION

VDDD(EP1)

1

TDO

2

L7

P external digital pad supply voltage 1 (+3.3 V)

N5

O test data output for boundary scan test; note 2

TDI

3

N6

I/pu test data input for boundary scan test; note 2

XTOUT

4

P4

O crystal oscillator output signal; auxiliary signal

VSS(XTAL)

5

XTALO

6

P5

P ground for crystal oscillator

P3

O 24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL

clock input of XTALI is used

XTALI

7

P2

I input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or

connection of external oscillator with TTL compatible square wave

clock signal

VDD(XTAL)

8

VSSA2

9

AI24

10

L8

M7, N7

P6

P supply voltage for crystal oscillator

P ground for analog inputs AI2n

I analog input 24

VDDA2

AI23

11

M8

P analog supply voltage for analog inputs AI2n (+3.3 V)

12

P7

I analog input 23

AI2D

13

P8

I differential input for ADC channel 2 (pins AI24, AI23, AI22 and AI21)

AI22

14

P9

I analog input 22

VSSA1

AI21

15

N8, N9

P ground for analog inputs AI1n

16

P10

I analog input 21

VDDA1

AI12

17

P analog supply voltage for analog inputs AI1n (+3.3 V)

18

P11

I analog input 12

AI1D

19

P12

I differential input for ADC channel 1 (pins AI12 and AI11)

AI11

20

P13

I analog input 11

AGND

21

N10

P analog ground connection

AOUT

22

M10

O do not connect; analog test output

VDDA0

23

N11

P analog supply voltage (+3.3 V) for internal Clock Generation Circuit

(CGC)

VSSA0

24

N12, N13

P ground for internal clock generation circuit

VDDD(EP2)

25

L9

P external digital pad supply voltage 2 (+3.3 V)

VSSD(EP1)

26

M13

P external digital pad supply ground 1

CE

27

N14

I/pu chip enable or reset input (with internal pull-up)

LLC

LLC2

RES

SCL

SDA

28

M14

O line-locked system clock output (27 MHz nominal)

29

L14

O line-locked 1⁄2 clock output (13.5 MHz nominal)

30

M12

O reset output (active LOW)

31

M11

I(/O) serial clock input (I2C-bus) with inactive output path

32

L12

I/O serial data input/output (I2C-bus)

VDDD(ICO1)

33

RTS0

34

RTS1

35

L11

P internal digital core supply voltage 1 (+3.3 V)

K13

O real-time status or sync information, controlled by subaddresses

L10

O 11H and 12H; see Section 15.2.18, 15.2.19 and 15.2.20

2004 Mar 03

7

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