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SAA4956TJ/V1

2.9-Mbit field memory with noise reduction

Philips Electronics 

Philips Semiconductors

2.9-Mbit field memory with noise reduction

Preliminary specification

SAA4956TJ

7.1.2 READ OPERATION

Read operations are controlled by the SRCK, RSTR, RE

and OE signals. A read operation starts with a reset read

address pointer (RSTR) operation, followed by a complete

cycle of the SRCK clock during which time RE and OE

must be held HIGH. Read operations between two

successive reset read operations must contain at least

20 SRCK read clock cycles while RE is HIGH.

7.1.2.1 Reset read: RSTR

The first positive transition of SRCK after RSTR goes from

LOW-to-HIGH resets the read address pointer to the

lowest address (−12 decimal; see Figs 11 and 12). If RE is

LOW, however, the reset read operation to the lowest

address will be delayed until the first positive transition of

SRCK after RE goes HIGH. RSTR set-up (tsu(RSTR)) and

hold (th(RSTR)) times are referenced to the rising edge of

SRCK (see Fig.11). The reset read operation may also be

asynchronously related to the SRCK signal if RE is LOW.

RSTR needs to stay LOW for a single SRCK cycle before

another reset write operation can take place.

7.1.2.2 Random read block access mode

The SAA4956TJ will enter random read block access

mode if the following signal sequence is applied to control

inputs RE and OE during the first four SWCK write clock

cycles after a reset read (see Fig.13):

1. At the 1st and 2nd positive transitions of SRCK,

OE must be LOW and RE must be HIGH

2. At the 3rd and 4th positive transitions of SRCK,

OE must be HIGH and RE must be LOW.

During this time, control signals RE and OE will function as

defined for normal operation. The Most Significant Bit

(MSB) of the block read address is applied to the OE input

pin at the 5th positive transition of SRCK. The remaining

12 bits of the 13-bit read block address must be applied, in

turn, to OE at the following 12 positive transitions of

SWCK. The Least Significant Bit (LSB) of the block

address is applied at the 17th positive transition of SRCK.

A read latency period of 20 additional SRCK clock cycles

is required before read access to the new block address is

possible. During this period, data is transferred from the

memory array to the serial read and parallel read registers

and the read pointer is set to the new block address.

Block address values between 0 and 6143 are valid.

Values outside this range must be avoided because invalid

block addresses can result in abnormal operation or a

lock-up condition. Recovery from lock-up requires a

standard reset read operation.

The data output pins are not controlled by the OE pin and

are forced into high impedance mode from the 3rd to

the 17th positive transition of SRCK. OE should be held

LOW during the read latency period. RE must remain LOW

from the 3rd positive transition of SRCK to the 20th read

latency SRCK clock cycle.

After the 20th read latency SRCK clock cycle, RE and OE

may be switched HIGH to prepare for reading new data

from the new address block at the next positive transition

of SRCK. The complete read block access entry sequence

is finished after the 20th read latency cycle.

The LOW-to-HIGH transition on RSTR required at the

beginning of the sequence should not be repeated.

Additional LOW-to-HIGH transitions on RSTR would

disable the read block address mode and reset the read

pointer.

7.1.2.3 Data outputs: Q0 to Q11 and read clock:

SRCK

The new data is shifted out of the data output registers on

the rising edge of the SRCK read clock provided RE and

OE are HIGH. Data output pins are low impedance if OE is

HIGH. If OE is LOW, the data outputs are high impedance

and the data output bus may be used by other devices.

Data output hold (th(Q)) and access times (tACC) are

referenced to the positive transition of SRCK. The output

data becomes valid after access time interval tACC (see

Fig.12).

Data output pins Q0 to Q11 are TTL compatible with the

restriction that when the outputs are high impedance, they

must not be forced higher than VDD(O) + 0.5 V or 5.0 V

absolute. The output data has the same polarity as the

incoming data at inputs D0 to D11.

7.1.2.4 Read enable: RE

RE is used to increment the read pointer. Therefore, RE

needs to be HIGH at the positive transition of SRCK. When

RE is LOW, the read pointer is not incremented. RE set-up

(tsu(RE)) and hold times (th(RE)) are referenced to the

positive edge of SRCK (see Fig.14).

7.1.2.5 Output enable: OE

OE is used to enable or disable data outputs Q0 to Q11.

The data outputs are enabled (low impedance) if OE is

HIGH. OE LOW disables the data output pins (high

impedance). Incrementing of the read pointer does not

depend on the status of OE. OE set-up (tsu(OE)) and hold

times (th(OE)) are referenced to the positive edge of SRCK

(see Fig.15).

1998 Dec 08

9

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