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SAA4956TJ/V1

2.9-Mbit field memory with noise reduction

Philips Electronics 

Philips Semiconductors

2.9-Mbit field memory with noise reduction

Preliminary specification

SAA4956TJ

7.1.3 POWER-UP AND INITIALIZATION

Reliable operation is not guaranteed until at least 100 µs

after power-up, the time needed to stabilize VDD within the

recommended operating range. After the 100 µs power-up

interval has elapsed, the following initialization sequence

must be performed: a minimum of 12 dummy read

operations (SRCK cycles) followed by a reset read

operation (RSTR), and a minimum of 12 dummy write

operations (SWCK) followed by a reset write operation

(RSTW). Read and write initialization may be performed

simultaneously.

If initialization starts earlier than the recommended 100 µs

after power-up, the initialization sequence described

above must be repeated, starting with an additional reset

read operation and an additional reset write operation after

the 100 µs start-up time.

7.1.4 OLD AND NEW DATA ACCESS

A minimum delay of 40 SWCK clock cycles is needed

before newly written data can be read back from memory

(see Fig.16). If a reset read operation (RSTR) occurs in a

read cycle before a reset write operation (RSTW) in a write

cycle accessing the same location, then old data will be

read.

Old data will be read provided a data read cycle begins

within 20 pointer positions of the start of a write cycle. This

means that if a reset read operation begins within

20 SWCK clock cycles after a reset write operation, the

internal buffering of the SAA4956TJ will ensure that old

data will be read out (see Fig.17).

New data will be read if the read pointer is delayed by

40 pointer positions or more after the write pointer.

Old data is still read out if the write pointer is less than or

equal to 20 pointer positions ahead of the read pointer

(internal buffering). A write pointer to read pointer delay of

more than 20 but less than 40 pointer positions should be

avoided. In this case, the old or the new data may be read,

or a combination of both.

In random read and write block access modes, the

minimum write-to-read new data delay of 40 SWCK clock

cycles must be inserted for each block.

7.1.5 MEMORY ARBITRATION LOGIC AND SELF-REFRESH

Since the data in the memory array is stored in DRAM

cells, it needs to be refreshed periodically. Refresh is

performed automatically under the control of internal

memory arbitration logic which is clocked by a free running

clock oscillator. The memory arbitration logic controls

memory access for read, write and refresh operations.

It uses the contents of the write, read and refresh address

counters to access the memory array to load data from the

parallel write register, store data in the parallel read

register, or to refresh stored data. The values in these

counters correspond to block addresses.

7.1.6 CASCADE OPERATION

If a longer delay is needed, the total storage depth can be

increased beyond 2949264 bits by cascading several

SAA4956TJs. For details see the interconnection and

timing diagrams (Figs 18 and 19).

The noise reduction function can be realized by enabling

this function with the NREN pin at one of the cascaded

SAA4956TJs.

7.1.7 TEST MODE OPERATION

The SAA4956TJ incorporates a test mode not intended for

customer use. If WE and RSTW are held HIGH

continuously for 1024 SWCK clock cycles, the

SAA4956TJ will enter test mode. It will exit test mode if WE

is LOW for a single SWCK cycle or if RSTW is LOW for

2 SWCK clock cycles.

1998 Dec 08

10

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