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SAA4956TJ

2.9-Mbit field memory with noise reduction

Philips Electronics 

Philips Semiconductors

2.9-Mbit field memory with noise reduction

Preliminary specification

SAA4956TJ

4 QUICK REFERENCE DATA

SYMBOL

PARAMETER

Tcy(SWCK) SWCK cycle time

Tcy(SRCK)

tACC

VDD

VDD(O)

VDD(P)

IDD(tot)

read cycle time (SRCK)

read access time after SRCK

supply voltage (pin 19)

supply voltage (pin 22)

supply voltage (pin 21)

total supply current

(IDD(tot) = IDD + IDD(O) + IDD(P))

CONDITIONS

NREN = LOW; see Fig.4

NREN = HIGH; see Fig.4

see Fig.11

see Fig.11

minimum read/write cycle;

outputs open

MIN.

26

52

26

−

3.0

3.0

3.0

−

TYP.

−

−

−

−

3.3

3.3

3.3

27

MAX.

−

150

−

21

3.6

3.6

5.5

70

UNIT

ns

ns

ns

ns

V

V

V

mA

1998 Dec 08

4

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