HM62G18512 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HM62G18512

8M Synchronous Fast Static RAM (512k-word × 18-bit)

Hitachi -> Renesas Electronics 

HM62G18512 Series

DC Characteristics (Ta = 0 to 70°C, [Tj max = 110°C], VDD = 3.3 V +10%, –5%)

Parameter

Symbol Min

Typ Max

Unit Notes

Input leakage current ILI

—

Output leakage current ILO

—

Standby current

I SBZZ

—

VDD operating current, IDD4

—

excluding output drivers

4 ns cycle

—2

—5

— 100

— 700

µA 1

µA 2

mA 3

mA 4

VDD operating current, IDD5

—

excluding output drivers

5 ns cycle

— 600

mA 4

Quiescent active power IDD2

—

supply current

— 200

mA 5

Output low voltage

VOL

Output high voltage

VOH

ZQ pin connect

RQ

resistance

VSS

VDDQ – 0.4

150

— VSS + 0.4

—

VDDQ

250 300

V6

V6

Ω

Output low current

I OL

(VDDQ/2)/[(RQ/5)–15%] — (VDDQ/2)/[(RQ/5)+15%] mA 7, 9

Output high current

I OH

(VDDQ/2)/[(RQ/5–4)+15%] — (VDDQ/2)/[(RQ/5–4)–15%] mA 8, 9

Notes: 1. 0 ≤ Vin ≤ VDDQ for all input pins (except VREF, ZQ, M1, M2 pin).

2. 0 ≤ Vout ≤ VDDQ, DQ in High-Z.

3. All inputs (except clock) are held at either VIH or VIL, ZZ is held at VIH, Iout = 0 mA, Spec is

guaranteed at 75°C junction temperature.

4. Iout = 0 mA, read 50%/write 50%, VDD = VDD max, VIN = VIH or VIL, Frequency = minimum cycle.

5. Iout = 0 mA, read 50%/write 50%, VDD = VDD max, VIN = VIH or VIL, Frequency = 3 MHz.

6. Minimum impedance push pull output buffer mode, IOH = –6 mA, IOL = 6 mA.

7. Measured at VOL = 1/2 VDDQ.

8. Measured at VOH = 1/2 VDDQ.

9. Output buffer impedance can be programmed by terminating the ZQ pin to VSS through a

precision resister (RQ). The value of RQ is five times the output impedance desired. The

allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between

150 Ω and 300 Ω. If the status of ZQ pin is open, output impedance is maximum. Maximum

impedance occurs with ZQ connected to VDDQ. The impedance update of the output driver

occurs when the SRAM is in High-Z. Write and Deselect operations will synchronously switch

the SRAM into and out of High-Z, therefore triggering an update. The user may choose to

invoke asynchronous G updates by providing a G setup and hold about the K clock to guarantee

the proper update. At power-up, the output impedance defaults to minimum impedance. It will

take 2048 cycles for the impedance to be completely updated if the programmed impedance is

much higher than minimum impedance.

8

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