HM62G18512 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HM62G18512

8M Synchronous Fast Static RAM (512k-word × 18-bit)

Hitachi -> Renesas Electronics 

HM62G18512 Series

Operation Table

ZZ SS G

SWE SWEa SWEb K

K

Operation

DQ (n) DQ (n + 1)

H

×

×

×

×

×

×

×

sleep mode

High-Z High-Z

L

H

×

×

×

×

L-H H-L Dead

×

(not selected)

High-Z

L

×

H

×

×

×

×

×

Dead

High-Z High-Z

(Dummy read)

L

L

L

H

×

×

L-H H-L Read

×

Dout

(a,b)0-8

L

L

×

L

L

L

L-H H-L Write a, b byte High-Z Din (a,b)0-8

L

L

×

L

L

H

L-H H-L Write a byte

High-Z Din (a)0-8

L

L

×

L

H

L

L-H H-L Write b byte

High-Z Din (b)0-8

Notes: 1. × means don’t care for synchronous inputs, and H or L for asynchronous inputs.

2. SWE, SS, SWEa to SWEb, SA are sampled at the rising edge of K clock.

3. Although differential clock operation is implied, this SRAM will operate properly with one clock

phase (either K or K) tied to VREF. Under such single-ended clock operation, all parameters

specified within this document will be met.

5

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