RS5C316 Просмотр технического описания (PDF) - RICOH Co.,Ltd.
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RS5C316 Datasheet PDF : 38 Pages
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RS5C316A/B
USAGES
1. Read Data (For the RS5C316A)
The real-time clock becomes accessible by switching the CE pin from the low level to high level to enable inter-
facing with the CPU and then inputting setting data (control bits and address bits) to the SIO pin in synchronization
with shift clock pulses from the SCLK pin. The input data are registered in synchronization with the falling edge of
the SCLK. When the data is read, the read cycle shall be set by control bits then registered data can be read out
from SIO pin in synchronization with the rising edge of the SCLK.
• Control bits
• Address bits
R/W: Establishes the read mode when set to 1, and the write mode when set to 0.
AD: Writes succeeding addressing bits (A3-A0) to the address register when set to 1 with the
DT bit set to 0 and performs no such write operation in any other case.
DT: Writes data bits to counter or register specified by the address register set just before
when set to 1 with the R/W and AD bits set equally to 0 and performs no such write oper-
ation in any other case.
A3-A0: Inputs the bits MSB to LSB in the address table describing the functions.
1.1 Read Cycle Flow
1. The CE pin is switched from “L” to “H”.
2. Four control bits (with the first bit ignored) and four read address bits are input from the SIO pin. At this time,
control bits R/W and AD are set equally to 1 while a control bit DT is set to 0. (see the SCLK 1A-8A)
3. The SIO pin enters the output mode at the rising edge of the shift clock pulse 2B from the SCLK pin while the
four read bits (MSB → LSB) at designated addresses are output at the rising edge of the shift clock pulse 5B.
(see the figure below)
4. Then, the SIO pin returns to the input mode at the rising edge of the shift clock pulse 1C. Afterwards control bits
and address bits are input at the shift clock pulses 1C in the same manner as at the shift clock pulse 1A.
5. At the end of read cycle, the CE pin is switched from “H” to “L” (after tCEH from the falling edge of the eighth
shift clock pulse from the SCLK pin). Following on read cycle, write operation can be performed by setting con-
trol bits in the write mode at the shift clock pulse 1C and later with the CE pin held at “H”.
CE
SCLK
Input to
SIO pin
1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C
Writing to shift
register
*
* R/W AD DT A3 A2 A1 A0
Control bits
Address bits
Setting of SIO Shifting data
pin in output
mode
(Hiz)
Setting of SIO
pin in input
mode
R/W AD
Output
from SIO
pin
(Hiz)
(Internal processing)
Setting of
control bits
– – – D3 D2 D1 D0
Writing to address
register
Read data
* * ) In the above figure, the “ ” mark indicates arbitrary data; the “–” mark indicates unknown data.
The “ ” mark indicates data which are available when the SIO pin is held at “H”, “L”, or Hiz level.
The diagonally shaded area of the CE and the SCLK pins indicate “H” or “L”.
(Hiz)
15
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