RS5C316 Просмотр технического описания (PDF) - RICOH Co.,Ltd.
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RS5C316 Datasheet PDF : 38 Pages
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RS5C316A/B
2.1-6 (CTFG)
The CTFG bit is set to 1 when interrupt pulses are output from the INTR pin held at the low level. There are two
interrupt modes selectable: the pulse mode (when the CT3 bit is set to 0) and the level mode (when the CT3 bit is set
to 1). The CTFG bit can be set only when the CT3 is set to 1. Setting the CTFG bit to 1 switches the INTR pin to the
low level while setting the CTFG bit to 0 turns off the INTR pin.
Interrupt cycle register
CT3
CT2
CT1
CT0
0
* *1
0
0
0
*
0
1
0
*
1
0
0
*
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
INTR output
OFF
ON
0.977ms
0.5s
1s
10s
1 minute
10 minutes
1 hour
1 day
1 week
1 month
Description
Interrupt halt
Fixing the INTR pin at low level
Cycle: 0.977ms (1/1024Hz) Duty 50% *2
Cycle: 0.5s (1/2Hz) *3
Every second *4
Every 10 seconds *4
(For display of second digits: 00, 10, 20, 30, 40 and 50)
Every minute (00 second) *4
Every 10 minutes (00 second) *4
(For display of minute digits: 00, 10, 20, 30, 40 and 50)
Every hour (00 minute and 00 second) *4
Every day (00 hour, 00 minute and 00 second a.m.) *4
Every week *4
(0 week, 0 hour, 00 minute and 00 second a.m.)
Every month *4
(1 day, 0 hour, 00 minute and 00 second a.m.)
* * 1) The symbol “ ” in the above table indicates 0 or 1.
*2)
0.977ms
CTFG
INTR
*3)
CTFG
INTR
*4)
CTFG
INTR
0.5s
0.488ms
Interrupt
Interrupt
Setting CTFG bit to 0
(Second count-up)(Second count-up)
10
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