HN58C65FP-25 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HN58C65FP-25

8192-word × 8-bit Electrically Erasable and Programmable CMOS ROM

Hitachi -> Renesas Electronics 

Block Diagram

VCC

High Voltage Generator

VSS

OE

CE

Control Logic and Timing

WE

A0

A4

Address

Buffer and

Latch

A5

A12

Y Decoder

X Decoder

HN58C65 Series

I/O0

I/O7 RDY/Busy

I/O Buffer

and

Input Latch

Y Gating

Memory Array

Data Latch

Mode Selection

Pin Mode

CE

OE

WE

RDY/Busy

Read

VIL

VIL

VIH

High-Z

Standby

VIH

X*1

X

High-Z

Write

VIL

VIH

VIL

High-Z to VOL

Deselect

VIL

VIH

VIH

High-Z

Write inhibit

X

X

VIH

X

VIL

X

High-Z

Data polling

VIL

VIL

VIH

VOL

Note: 1. X = Don’t care

I/O

Dout

High-Z

Din

High-Z

—

Data out (I/O7)

3

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