![](/html/Renesas/583406/page2.png)
RD74LVC1G79
Function Table
Inputs
CLK
D
↑
H
↑
L
L
X
H: High level
L: Low level
X: Immaterial
↑: Low to high transition
Q0: Level of Q before the indicated steady input conditions was established.
Pin Arrangement
0.7 mm
Height 0.4 mm
0.4 mm pitch
0.17 mm 5–Ball (WP) GND
34
Q
Output Q
H
L
Q0
CLK
2
D
15
VCC
Pin#1 INDEX
(Bottom view)
(Top view)
Logic Diagram
CLK
C
C
C
TG
Q
C
C
D
TG
TG
C
C
TG
C
C
C
Rev.1.00 Feb 23, 2006 page 2 of 8