PMB2341 Просмотр технического описания (PDF) - Infineon Technologies

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PMB2341

10-pin Single PLL

Infineon Technologies 

Confidential

PMB 2341

preliminary

Applications

4.1 Programing

General information:

Programming of the IC is done via the 3 wire serial data interface consisting of a clock

line, data line and an enable line. Data are shifted into the device with every rising CLK

edge and are overtaken into internal registers with the rising edge of EN according to the

schematic timing diagram shown in Figure 4-1.

CLK

DAT

EN

latch data into

internal register

Figure 4-1 Schematic bus signal timing

Depending on the desired functional units to be programmed, several serial data formats

exist. A common fact is that all multibit values are ordered in little endian notation in the

bitstream meaning their MSB is sent first.

Every bus cycle starts with the dedicated data bits followed by at least 1 register address

bit and is terminated with two device address bits. In chapter 4.2 Register, Data format

the available data formats are explained.

The short control data format allows a fast PD-current change.

The long control data format allows the programming of 4 different PD-output current

modes for the PLL, polarity setting of the PD-output signals, 2 standby modes, test mode

select and the prescaler divide ratio.

The A/N-counter data format contains the A/N-counter values, the multifunctional output

bit and standby mode switch bits.

The R-counter data format contains the R-counter values and PLL programming mode

switch bit.

The PLL is programmed in an asynchronous mode: The serial data is written directly to

the data registers of the addressed counter with the enable pulse. As each counter is

loading the new starting value after it is decremented to „zero“, the counters changes

therefore their counter values asynchronously to the others.

Wireless Components

4-2

Specification, February 2000

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