W83194R-37 Просмотр технического описания (PDF) - Winbond

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W83194R-37

100 MHZ AGP CLOCK FOR VIA CHIPSET

Winbond 

Preliminary W83194R-37/-58

8.3.2 Register 1: CPU, 48/24 MHz Clock Register (1 = Active, 0 = Inactive), continued

BIT @POWERUP

PIN

DESCRIPTION

3

1

40 CPUCLK3 (Active/Inactive)

2

1

41 CPUCLK2 (Active/Inactive)

1

1

43 CPUCLK1 (Active/Inactive)

0

1

44 CPUCLK0 (Active/Inactive)

8.3.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive)

BIT @POWERUP

7

x

6

1

5

1

4

1

3

1

2

1

1

1

0

1

PIN

DESCRIPTION

-

Reserved

7

PCICLK_F (Active/Inactive)

15 AGP0 (Active/Inactive)

14 PCICLK4 (Active/Inactive)

12 PCICLK3 (Active/Inactive)

11 PCICLK2 (Active/Inactive)

10 PCICLk1 (Active/Inactive)

8

PCICLK0 (Active/Inactive)

8.3.4 Register 3: SDRAM Clock Register (1 = Active, 0 = Inactive)

BIT @POWERUP

7

1

6

1

5

1

4

1

3

1

2

1

1

1

0

1

PIN

DESCRIPTION

28 SDRAM7 (Active/Inactive)

29 SDRAM6 (Active/Inactive)

31 SDRAM5 (Active/Inactive)

32 SDRAM4 (Active/Inactive)

34 SDRAM3 (Active/Inactive)

35 SDRAM2 (Active/Inactive)

37 SDRAM1 (Active/Inactive)

38 SDRAM0 (Active/Inactive)

8.3.5 Register 4: Additional SDRAM Clock Register (1 = Active, 0 = Inactive)

BIT @POWERUP

7

x

6

x

PIN

-

Reserved

-

Reserved

DESCRIPTION

Publication Release Date: April 1999

-9-

Revision A1

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