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PI6C180BV
(Rev.:2000)

Precision 1-18 Clock Buffer

Pericom Semiconductor 

PI6C180B

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2-Wire I2C Control

The I2C interface permits individual enable/disable of each clock

output and test mode enable.

The PI6C180B is a slave receiver device. It can not be read back. Sub

addressing is not supported. All preceding bytes must be sent in

order to change one of the control bytes.

Every bite put on the SDATA line must be 8-bits long (MSB first),

followed by an acknowledge bit generated by the receiving device.

During normal data transfers SDATA changes only when SCLOCK

is LOW. Exceptions: A HIGH to LOW transition on SDATA while

SCLOCK is HIGH indicates a “start” condition. A LOW to HIGH

transition on SDATAwhile SCLOCK is HIGH is a “stop” condition

and indicates the end of a data transfer cycle.

Each data transfer is initiated with a start condition and ended with

a stop condition. The first byte after a start condition is always a

7-bit address byte followed by a read/write bit. (HIGH = read from

addressed device, LOW= write to addressed device). If the device’s

own address is detected, PI6C180B generates an acknowledge by

pulling SDATA line LOW during ninth clock pulse, then accepts

the following data bytes until another start or stop condition is

detected.

Following acknowledgement of the address byte (D2), two more

bytes must be sent:

1. “Command Code” byte, and

2. “Byte Count” byte.

Although the data bits on these two bytes are “don’t care,” they

must be sent and acknowledged.

Byte1: SDRAM Active/Inactive Register

(1 = enable, 0 = disable)

Bit Pin #

Description

Bit 7 45 SDRAM15 (Active/Inactive)

Bit 6 44 SDRAM14 (Active/Inactive)

Bit 5 41 SDRAM13 (Active/Inactive)

Bit 4 40 SDRAM12 (Active/Inactive)

Bit 3 36 SDRAM11 (Active/Inactive)

Bit 2 35 SDRAM10 (Active/Inactive)

Bit 1 32 SDRAM9 (Active/Inactive)

Bit 0 31 SDRAM8 (Active/Inactive)

Byte2: Optional Register for Possible Future

Requirements (1 = enable, 0 = disable)

Bit Pin #

Description

Bit 7 28 SDRAM17 (Active/Inactive)

Bit 6 21 SDRAM16 (Active/Inactive)

Bit 5

(Reserved)

Bit 4

(Reserved)

Bit 3

(Reserved)

Bit 2

(Reserved)

Bit 1

(Reserved)

Bit 0

(Reserved)

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature ............................................................. –65°C to +150°C

Ambient Temperature with Power Applied .............................. –0°C to +70°C

3.3V Supply Voltage to Ground Potential .............................. –0.5V to +4.6V

DC Input Voltage .................................................................... –0.5V to +4.6V

Note:

Stresses greater than those listed under MAXIMUM

RATINGS may cause permanent damage to the

device. This is a stress rating only and functional

operation of the device at these or any other conditions

above those indicated in the operational

sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended

periods may affect reliability.

Supply Current (VDD = +3.465V, CLOAD = Max.)

Symbol

Parameter

Test Condition

Min. Typ. Max. Units

IDD

Supply Current

BUF_IN = 0 MHz

IDD

Supply Current

BUF_IN = 66.66 MHz

3

230 mA

IDD

Supply Current

BUF_IN = 100.0 MHz

360

3

PS8468 05/03/00

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