PCK2021DGG Просмотр технического описания (PDF) - Philips Electronics
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PCK2021DGG Datasheet PDF : 15 Pages
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Philips Semiconductors
CK00 (100/133 MHz) spread spectrum differential
system clock generator
Product data
PCK2021
AC ELECTRICAL CHARACTERISTICS
VDD3 = 3.3 V ±5%; fcrystal = 14.31818 MHz
Host clock outputs
Tamb = 0 to +70 °C; see Figure 1 for waveforms and Figure 6 for test setup.
LIMITS
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
MIN
MAX
MIN
MAX
tPERIOD
Abs Min Period
HOST CLK average period
Absolute minimum host clock period
7.5
7.35
7.65
N/A
10.0
9.85
10.2
N/A
tRISE
tFALL
tJITTER
DUTY CYCLE
HOST CLK rise time
HOST CLK fall time
HOST_CLK cycle-to-cycle jitter
Output duty cycle
175
700
175
700
175
700
175
700
—
150
—
150
45
55
45
55
tSKEW
HOST CLK pin-to-pin skew
Vcrossover
REFER TO NOTES ON PAGE 10.
—
45% VOH
150
55% VOH
—
45% VOH
110
55% VOH
UNITS
NOTES
ns
11, 14, 19
ns
11, 14, 19
ns
11, 15, 19
ps
11, 15, 19
ps 11, 12, 14, 19
%
11, 14, 19
ps
11, 14, 19
V
11, 14, 19
USB clock output, 48MHz
Tamb = 0 to +70 °C; lump capacitance test load = 20 pF
SYMBOL
PARAMETER
f
Frequency, actual
fD
tRISE
tFALL
tJITTER
DUTY CYCLE
Deviation from 48 MHz
3V48MHZCLK rise time
3V48MHZCLK fall time
Cycle-to-cycle jitter
Output duty cycle
REFER TO NOTES ON PAGE 10.
LIMITS
48 MHz MODE
MIN
MAX
48.000
–0
+167
1.0
4.0
1.0
4.0
—
450
45
55
UNITS
MHz
ppm
ns
ns
ps
%
NOTES
4
4
8, 19
8, 19
17, 19
17, 19
PCI Outputs
Tamb = 0 to +70 °C
SYMBOL
tPERIOD
tHIGH
tLOW
tRISE
tFALL
DUTY CYCLE
Period
High time
Low time
Rise time
Fall time
Duty cycle
tJITTER
Cycle-to-cycle jitter
tSKEW
Pin-to-pin skew
REFER TO NOTES ON PAGE 10.
PARAMETER
LIMITS
MIN
MAX
30.0
N/A
12.0
N/A
12.0
N/A
0.5
2.0
0.5
2.0
45
55
—
200
—
150
UNITS
ns
ns
ns
ns
ns
%
ps
ps
NOTES
2, 3, 9, 19
5, 10, 19
6, 10, 19
8, 19
17, 19
17, 19
17, 19
2
2001 Oct 11
8
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