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PCD6001

Digital telephone answering machine chip

Philips Electronics 

Philips Semiconductors

Digital telephone answering machine chip

Product specification

PCD6001

9.3 Real-Time Clock generation

The Real-Time Clock (RTC) divider provides a 1 minute

timing signal which is available as an interrupt to the

microcontroller. The RTC_CLK input clock is always

active, whether the PLL is active or not. Thus the complete

chip can be set into Power-down mode (but not System-off

mode), where the microcontroller can be woken up by the

RTC to maintain the values for date and time. The

RTC_CLK is directly derived from the EMG_CLK input

clock signal.

Figure 6 shows the RTC clock generation. To divide a

3.456 or a 3.580 MHz clock into a 1 minute RTC signal a

28 bit counter is required to count 60 × 3.456 × 106 clock

periods. To determine the number of most significant bits

of this counter required for an accurate RTC, the maximum

allowed time deviation per month and the crystal accuracy

need to be taken into account. The LSB of the 28 counter

has an accuracy of 1/(60 × 3.456 × 106) = 0.005

parts-per-million (ppm). Since a normal crystal accuracy is

about 10 ppm it is tolerable to have only the 17 MSB of the

counter available (10/0.005 = 2000, which implies that the

11 LSB can be disregarded), as shown in Fig.6.

If one month is set to 30 × 24 × 60 × 60 = 2.6 × 106

seconds, 10 ppm deviation equals 26 seconds per month

or about 5 minutes per year.

Since there are 2 possible RTC_CLK values, 3.580 and

3.456 MHz, there are 2 comparators selectable for the

RTC; COMP_3.580 and COMP_3.456. The nominal value

of these comparators are (11 LSB are set to logic 0):

COMP_3.580: CCD2800H (RTCON = A5H)

COMP_3.456: C5C1000H (RTCON = 82H).

In Section 9.2 the conditions for the RTC_MODE signal

are described.To allow connection of various crystals or

ceramic resonators, as well as to provide adjustment of the

RTC clock according to the crystal tolerance, 8 of the 17

most significant bits of the comparators are programmable

via the SFR register RTCON. The binary values of the

comparators are then as shown in Table 11.

Since the accuracy of Q11 is 10 ppm, with the adjustment

of the RTC via RTCON an accuracy of ±5 ppm can be

achieved. For an RTC pulse every 1 minute the outer limits

of the crystal frequency inputs which can be connected

are:

COMP_3.580 (max): CCFF800H → 3.582600 MHz

COMP_3.580 (min): CC80000H → 3.573897 MHz.

COMP_3.456 (max): C5FF800H → 3.460267 MHz

COMP_3.456 (min): C580000H → 3.451563 MHz.

The default value of RTCON for an input frequency

3.58 MHz is A5H and for an input frequency of 3.456 MHz

is 82H.

Table 11 Comparator contents

Q27

Q18

Q11

COMP_3.580 1 1 0 0 1 1 0 0 1 x x x x x x x x

COMP_3.456 1 1 0 0 0 1 0 1 1 x x x x x x x x

bit 7

←RTCON→

bit 0

handbook, full pagewidth

EMG_CLK

Q11 to Q27

28 BIT

RIPPLE

17

Q10

Q0

synch_reset

RTC_MODE

0: RTC_CLK = 3.456 MHz

1: RTC_CLK = 3.580 MHz

17

COMP_3.456

0

17

COMP_3.580

1

RTC_event

MGM770

Fig.6 Real-Time Clock (RTC) generation.

2001 Apr 17

19

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