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PCD6001

Digital telephone answering machine chip

Philips Electronics 

Philips Semiconductors

Digital telephone answering machine chip

Product specification

PCD6001

9 TICB - GENERATION AND SELECTION OF

SYSTEM CLOCKS

The TICB generates the clocks for all digital chip blocks,

and controls the on/off switching of these blocks by using

clock gating. The TICB is controlled via the microcontroller

SFR registers SYMOD, CKCON and SPCON. The TICB

contains:

• An input section to adapt to different input clock rates

• A clock generation section

• A clock selection section

• The Real-Time Clock for a 1 minute interrupt generation

• The microcontroller interrupt timers (FS_event and

TIME_event) and the DSP interrupt timer (FS1) to

respectively synchronize the microcontroller and DSP

processes.

9.1 Microprocessor, DSP, CODEC and IOM clock

generation

Figure 4 shows the TICB input section and the clock

generation section.

The clock generation section contains a PLL to generate

the clock rates which are higher then the input clock rate.

With the input section, a wider variety of input clock

frequencies can be adapted to the input frequency values

needed by the PLL (3.456 or 3.580 MHz).

In order to save power the PLL can be switched off. This

should however only be done when the chip is in the

Emergency mode. When switching on the PLL, it takes

40 µs (173 emergency clock periods) until the clock

frequencies are derived from the PLL output.

Table 2 gives a description of the signals and their values

for a crystal frequency of 3.456 and 3.580 MHz.

The clock generation section also contains logic to

synchronize the CODEC timing signals and the DSP and

microcontroller interrupt timers to an external Frame

Sync. (FSC). This synchronization is only activated when

using the IOM in Slave mode. If the IOM is activated in

Master mode, the TICB generates the DCK and

FSC signals from CLK28.

Some of the clock signals can be made available as

general purpose clock, for various peripherals needing a

clock source such as an PCA1070 line interface. This

general purpose clock (GPC) signal is an alternative

output of P4.5 and can be turned on with ALTP bit 3. With

ALTP bit 2, the source for GPC can be defined. The GPC

source is EMG_CLK (normally 3.58 MHz) when bit 2 is

logic 0 and the GPC source is µC_CLK when bit 2 is set to

logic 1. As a spike-free GPC is not guaranteed when

switching between these clocks, it is recommended to first

set the clock source before switching on the GPC. The

ALTP register is described in more detail in Section 16.2.

2001 Apr 17

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