GLT6200L16L-55FG Просмотр технического описания (PDF) - G-Link Technology
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GLT6200L16L-55FG Datasheet PDF : 13 Pages
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G-LINK
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input and Output Timing
Reference Level
Output Load Condition
CL = 30pf + 1TTL Load
0.4V to 2.4V
5 ns
1.4V
GLT6200L16
Ultra Low Power 128k x 16 CMOS SRAM
May 2001(Rev. 2.3)
AC Test Loads and Waveforms
TTL
CL*
*Including Scope and Jig Capacitance
Read Cycle (9)( Vcc=2.7V to 3.6V, TA = -25°C to 85°C )
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold from address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
BLE , BHE Enable to Output in Low-Z
BLE , BHE Disable to Output in High-Z
BLE , BHE Access Time
Symbol
tRC
tAA
tACE
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tBLZ
tBHZ
tBA
55
Min Max
55
55
55
35
10
10
25
5
25
5
25
35
70
Min Max
70
70
70
40
10
10
30
5
25
5
25
40
85
Min Max
85
85
85
40
10
10
35
5
30
5
30
85
Unit Note
ns
ns
ns
ns
ns
ns 4,5
ns 3,4,5
ns
ns
ns 4,5
ns 3,4,5
ns
Timing Waveform of Read Cycle 1 (Address Controlled)
tRC
Address
tOH
tAA
DOUT
Previous Data Valid
Data Valid
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
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G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
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