EM565161 Просмотр технического описания (PDF) - Etron Technology

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EM565161

512K x 16 Low Power SRAM

Etron Technology 

Et r onT ec h

Write Cycle4

(UB#, LB# Controlled)(See Note 4)

Address

tAS

W E#

CE1#

tW C

tW P

tCW

EM565161

tW R

CE2

tCW

tBW

UB# , LB#

tBLZ tW HZ

DOUT

tLZ

tDS

tDH

DIN

(See Note 5)

VALID DATA IN

Note:

1. WE# remains HIGH for the read cycle.

2. If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high

impedance.

3. If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain at

high impedance.

4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance.

5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be

applied.

Preliminary

10

Rev 0.9

Jan 2002

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