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MC74HC4024D

7-Stage Binary Ripple Counter

Motorola => Freescale 

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

7-Stage Binary Ripple Counter

High–Performance Silicon–Gate CMOS

The MC74HC4024 is identical in pinout to the standard CMOS MC14024.

The device inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

This device consists of 7 master–slave flip–flops. The output of each

flip–flop feeds the next and the frequency at each output is half that of the

preceding one. The state of the counter advances on the negative going

edge of the Clock input. Reset is asynchronous and active–high.

State changes of the Q outputs do not occur simultaneously because of

internal ripple delays. Therefore, decoded output signals are subject to

decoding spikes and may have to be gated with the Clock of the HC4024 for

some designs.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 206 FETs or 51.5 Equivalent Gates

LOGIC DIAGRAM

CLOCK 1

12 Q1

11 Q2

9 Q3

6 Q4

5 Q5

4 Q6

3 Q7

RESET 2

PIN 14 = VCC

PIN 7 = GND

PINS 8, 10 AND 13 = NO CONNECTION

MC74HC4024

14

1

14

1

N SUFFIX

PLASTIC PACKAGE

CASE 646–06

D SUFFIX

SOIC PACKAGE

CASE 751A–03

ORDERING INFORMATION

MC74HCXXXXN Plastic

MC74HCXXXXD SOIC

PIN ASSIGNMENT

CLOCK 1

RESET 2

Q7 3

Q6 4

Q5 5

Q4 6

GND 7

14 VCC

13 NC

12 Q1

11 Q2

10 NC

9 Q3

8 NC

NC = NO CONNECTION

Clock

X

FUNCTION TABLE

Reset

L

L

H

Output State

No Change

Advance to Next State

All Outputs are Low

10/95

© Motorola, Inc. 1995

1

REV 6

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