AD9802 Просмотр технического описания (PDF) - Analog Devices

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AD9802

CCD Signal Processor For Electronic Cameras

Analog Devices 

AD9802

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CCD SIGNAL

(DELAYED TO MATCH

ACTUAL SAMPLING

EDGE)

N

N+2

N+4

N+1

N+3

SHD

SHP

ACTUAL

tID

SAMPLING

EDGE

OBSOLETE ADCCLK

DIGITAL OUT

35ns 35ns

tOD

tH

OUTPUT LOAD CL = 20pF

OUTPUT DELAY tOD = 15ns

HOLD TIME tH = 2ns

INTERNAL CLOCK DELAY tID = 3ns

LATENCY = 5 CYCLES

Figure 12. Timing Diagram

SHP

DATA N–1

DATA N

SHD

PRE-ADC

OUTPUT LATCH

PRE-ADC

OUTPUT LATCH

DATA TRANSITION

ADCCLK

5ns

10ns

5ns

20ns

INHIBITED PERIOD

FOR ADCCLK

RISING EDGE

RISING EDGE

ANYWHERE IN

THIS PERIOD OK

Figure 13. ADCCLK Timing Edge

REV. 0

–7–

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