MT8979 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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MT8979 Datasheet PDF : 34 Pages
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MT8979
Data Sheet
Pin Description (continued)
Pin #
DIP PLCC
26 42
27 44
28 1
14 6,8,
22
Name
F0i
IC
VDD
VSS
Description
Frame Pulse Input: The ST-BUS frame synchronization signal which defines the
beginning of the 32 channel frame.
Internal Connection: Tie to VSS (Ground) for normal operation.
Positive Power Supply Input (+5 Volts).
Negative Power Supply Input (Ground).
Functional Description
The MT8979 is a CEPT trunk digital link interface conforming to CCITT Recommendation G.704 for PCM 30 and
I.431 for ISDN. It includes features such as: insertion and detection of synchronization patterns, optional cyclical
redundancy check and far end error performance reporting, HDB3 decoding and optional coding, channel
associated or common channel signalling, programmable digital attenuation and a two frame received elastic
buffer. The MT8979 can also monitor several conditions on the CEPT digital trunk, which include, frame and
multiframe synchronization, received all 1’s alarms, data slips as well as framing and CRC errors, both near and
far end.
The system interface to the MT8979 is a TDM bus structure that operates at 2048 kbit/s known as the ST-BUS.
This serial stream is divided into 125 µs frames that are made up of 32 x 8 bit channels.
The line interface to the MT8979 consists of split phase unipolar inputs and outputs which are supplied from/to a
bipolar line receiver/driver, respectively.
Frame
15
Frame
0
2.0 ms
••••••••
Frame
14
Frame
15
Frame
0
Timeslot
0
Timeslot
1
••••
Most
Significant
Bit (First)
Bit
1
Bit
2
Bit
3
125 µs
Bit Bit Bit
4
5
6
(8/2.048) µs
Timeslot
30
Timeslot
31
Least
Bit Bit Significant
7
8 Bit (Last)
Figure 3 - CEPT Link Frame & Multiframe Format
CEPT Interface
The CEPT frame format consists of 32, 8 bit timeslots. Of the 32 timeslots in a frame, 30 are defined as
information channels, timeslots 1-15 and 17-31 which correspond to telephone channels 1-30. An additional
voice/data channel may be obtained by placing the device in common channel signalling mode. This allows use of
timeslot 16 for 64 kbit/s common channel signalling.
4
Zarlink Semiconductor Inc.
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