MT8979 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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MT8979 Datasheet PDF : 34 Pages
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MT8979
Data Sheet
Frame Alignment Error Counter
The MT8979 provides an indication of the bit error rate found on the link as required by CCITT Recommendation
G.703. The ERR bit (Bit 5 of MSW1) is used to count the number of errors found in the frame alignment signal and
this can be used to estimate the bit error rate. The ERR bit changes state when 16 errors have been detected in
the frame alignment signal. This bit can not change state more than once every 128 ms, placing an upper limit on
the detectable error rate at approximately 10-3. The following formula can be used to calculate the BER:
BER= 16* number of times ERR bit toggles
7 * 4000 * elapsed time in seconds
where:
7 - is the number of bits in the frame alignment signal (0011011).
16 - is the number of errored frame alignment signals counted between changes of state of the ERR bit.
4000 - is the number of frame alignment signals in a one second interval.
This formula provides a good approximation of the BER given the following assumptions:
1. The bit errors are uniformly distributed on the line. In other words, every bit in every channel is equally
likely to get an error.
2. The errors that occur in channel 0 are bit errors. If the first assumption holds and the bit error rate is
reasonable, (below 10-3) then the probability of two or more errors in seven bits is very low.
Attenuation ROM
All transmit and receive data in the MT8979 is passed through the digital attenuation ROM according to the values
set on bits 5 - 0 of data channels in the control stream (CSTi0). Data can be attenuated on a per-channel basis
from 1 to -6 dB for both Tx and Rx data (refer Table 2).
Digital attenuation is applied on a per-channel basis to the data found one channel after the control information
stored in the control channel CSTi0, i.e., control stream 0 channel 4 contains the attenuation setting for data stream
(DSTo) channel 5.
Signalling Bit RAM
The A, B, C, & D Bit RAM is used to retain the status of the per-channel signalling bits so that they may be
multiplexed into the Control Output Stream (CSTo). This signalling information is only valid when the module is
synchronized to the received data stream. If synchronization is lost, the status of the signalling bits will be retained
for 6.0 ms provided the signalling debounce is active.
Integrated into the signalling bit RAM is a debounce circuit which will delay valid signalling bit changes for 6.0 to 8.0
ms. By debouncing the signalling bits, a bit error will not affect the call in progress. (See Table 3, bits 3-0 of
channel 15 on the CSTi0 line.)
CEPT PCM 30 Format MUX
The CEPT Link Multiplexer formats the data stream corresponding to the CEPT PCM 30 format. This implies that
the multiplexer will use timeslots 1 to 15 and 17 to 31 for data and uses timeslots 0 & 16 for the synchronization and
channel associated signalling.
The frame alignment or non-frame alignment signals for timeslot zero are sourced by the control stream input
CSTi1 channel 16 and 17, respectively. The most significant bit of timeslot zero will optionally contain the cyclical
redundancy check, CRC multiframe pattern and Si bits used for far-end CRC monitoring.
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