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MSM7503

Multi-Function PCM CODEC

Oki Electric Industry 

¡ Semiconductor

MSM7503

BD

Input to the D bit (2-bit sequence at 16 kbps) of line signals transmitted from the T1N and T2N

pins. When the BDS control pin is in "0", this pin enters the synchronous mode and data must be

input to this pin synchronizing with CLK2 (16 kHz).

When the BDS control pin is set to "1", this pin enters the asynchronous data input mode and the

asynchronous data of 11 bits including the start bit and stop bit can be input at data rate of 16 kbps.

BDS

Control signal input for selection of the synchronous mode or asynchronous mode for control

data (D-bit) input.

When being at "0" level, this pin enters the synchronous data input mode, when being at "1" level,

this pin enters the asynchronous data input mode.

PS

Monitoring signal output for the state of the ping-pong transmission. When frames are

synchronized (in normal operation) after receiving more than three consecutive frame synchronous

signals which are included in the line receive signal sequence, this pin outputs "1".

Otherwise, this pin outputs "0". PS is an output of an open drain type with pulled-up resistance

of about 10 kW.

X1, X2

CLK oscillator circuit input and output. X1 is input and X2 is output. A crystal oscillator of 8.192

MHz should be connected between X1 and X2. If the frequency deviation in CLK oscillation is

great with respect to the receive data rate, the noise of the CODEC increases. The oscillation

frequency deviation in CLK should be kept in ±20 ppm or less.

13/41

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