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MSM7503 Просмотр технического описания (PDF) - Oki Electric Industry

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MSM7503
OKI
Oki Electric Industry OKI
MSM7503 Datasheet PDF : 41 Pages
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¡ Semiconductor
MSM7503
SYNC
Synchronous signal (8 kHz) output.
This synchronous signal is generated by dividing the oscillator output of 8.192 MHz, applying
the frame synchronous bit included in the line signal as a reference phase. This signal also sent
to the tone generator and the CODEC inside the device. All timing signals of the CODEC are
synchronized by this signal.
CLK1
64 kHz CLK signal output synchronized to the SYNC signal output.
This signal is connected to the CODEC inside the device and is used as a bit clock for receiving
and sending the PCM I/O data from and to the ping-pong transmission interface. When an
external signal is input to the BHW pin, or when the FHW pin outputs signals for the external
circuit, the timing should be set by the CLK1 signal. This signal is always output in the power ON
mode.
CLK2
16 kHz CLK signal output synchronized to the SYNC signal output.
This signal can be used for the input or output of the control signal (BD input or FD output) of
16 kbps. This signal is always output in the power ON mode.
CLK3
CLK signal output of 256 kHz synchronized to the SYNC signal.
This signal can be used when the control signal of 16 kHz is input or output from or to the external
device by the start-stop synchronization. This signal is always output in the power ON mode.
CLC
Control signal input for phase-inverting the 256 kHz CLK signal which is output form the CLK3
pin.
If the reference phase is set by setting CLC to "0", the CLK signal of 256 kHz is phase-inverted
against the reference phase by setting CLC to "1".
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