IDT49C466 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT49C466 Datasheet PDF : 27 Pages
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IDT49C466/A Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
MD
LATCH OUT
BEn = 0 => Path A
BEn = 1 => Path B
64
64
64
BE0-7
PATH B
64
SD
LATCH IN
WRITE BUFFER
PATH A
BYTE
MUX
M
64
U
X
64
M
U
8
X
Figure 1. Byte Merge
COMMERCIAL TEMPERATURE RANGES
MD BUS
SD
LATCH OUT
64
WBSEL
2617 drw 05
Memory Read
During a memory read, data and the corresponding input
checkbits are read from the MD bus and CBI0-7, respectively.
The memory and checkbit data may both be latched as they
come in (MD Latch In and MD Checkbit latch) by the MDILE
signal. Memory data is sent to the MD checkbit generator
(where checkbits corresponding to the input data are gener-
ated) and to the error correct circuitry. The generated checkbits
are X-ORed with the input checkbits to produce the syndrome
word. This is sent to the error correction circuitry which
generates the corrected data (normal mode). The corrected
data is output to the SD bus via either of two data paths. When
RBSEL is LOW, data flows through MD Latch Out. Pulling
MDOLE HIGH latches this data. The output buffer is enabled
by asserting SOE (=0) and BE0-7 (=1). Corrected data can be
written back to memory by enabling the MD output buffer. In
order to ensure selection of the write back path (Path B in
figure 1) at the byte mux, BEO-7 should be all 1's while
WBSEL = 0. If WBSEL = 1, buffered BEO-7 from the output
of the write FIFO controls the byte mux.
If the read FIFO (RFIFO) is selected (RBSEL HIGH), data
is clocked into the FIFO (Read_FIFO Write) when RBEN is
LOW, on the rising edge of MCLK. RBFF is asserted when the
RFIFO is full and this inhibits further write attempts to the
RFIFO (see section on "Clock Skew" and "R/W FIFO opera-
tion at Boundaries"). Data is clocked out of the FIFO
(Read_FIFO Read) when RBREN is LOW on the rising edge
of SCLK. RBEF is asserted when the RFIFO is empty and this
inhibits further read attempts (see section on "Clock Skew")
from the RFIFO.
Note: In case of multiple error SD should be ignored in correct
mode
Clock Skew
A skew between the read and write clocks, as specified by
tskew, is recommended. This specification is not a stringent
one, in the manner of setup and hold times, but is important in
preempting latencies at FIFO boundaries. For example –
When a word is written to an empty FIFO, there is a finite delay
before the FIFO is recognized as no longer being empty and
hence allowing a read from the same FIFO. Similarly when a
word is read from a full FIFO, there is a delay before a write can
successfully be attempted. The tskew specification accounts
for these cases. During cycles other than on full/empty FIFO
boundaries, the clock skew is not required and the device
functions correctly even when the reads and writes occur
simultaneously. If the tskew specification is ignored and SCLK
and MCLK were permanently tied together, there is an extra
cycle latency in the cases mentioned above. Clock skew
violation is illustrated in Figure 13.
FIFO Write Latency
The first data written to either of the (read or write) FIFOs,
after the FIFO is reset, suffers a single clock latency. Data that
is set-up with respect to the first clock is ignored and the data
that is set-up with respect to the second clock edge after the
reset, is stored as the first data in the FIFO (Refer to Figures
9 and 10). The empty-flag is deasserted after this second clock
edge and 15 more data words (in a 16 deep configuration) can
be written to the FIFO after this.
The latency can be reduced or eliminated by providing a
"dummy" or "set-up" clock edge before the actual write to the
FIFO. The dummy write clock can be provided any time after
reset and before the next buffer write operation takes place.
The latency described here (shown in Figures 10 and 13)
occurs only after a FIFO reset. In other cases where the FIFO
becomes empty there is no latency.
11.7
8
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