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IDT49C466

64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

Integrated Device Technology 

IDT49C466/A Flow-thruEDC™

ERROR DETECTION AND CORRECTION UNIT

COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION

Pin Name

I/O

Data Buses

SD0-63

I/O

MD0-63

I/O

CBI0-7

I

CBSYN0-7

O

P0-7

I/O

Control Inputs

SOE

I

BE0-7

I

MOE

I

MDILE

I

MDOLE

I

SDOLE

I

SDILE

I

WBSEL

I

WBEN

I

WBREN

I

RS0-1

I

Description

System Data Bus: is a bidirectional 64-bit bus interfacing to the system or CPU. When System Output

Enable, SOE, is HIGH or Byte Enable, BE0-7, is LOW, data can be input. When System Output Enable,

SOE, is LOW and Byte Enable, BE0-7, is HIGH, the SD bus output drivers are enabled.

Memory Data Bus: is a bidirectional 64-bit bus interfacing to the memory. During a read cycle, (MOE

HIGH) memory data is input for error detection and correction. Data is output on the Memory Data

Bus, when MOE is LOW.

Check Bit Inputs: interface to the check bit memory.

Check Bit/Syndrome Output: When MOE is LOW the generated check bits are output. When

CBSEL is HIGH and MOE is HIGH, the syndrome bits are output. The bus is tristated when MOE =

1 and CBSEL = 0.

Parity for bytes 0 to 7: These pins are parity inputs when the corresponding Byte Enable (BE) is LOW

or SOE is HIGH, and are used to generate the parity error signal (PERR). These pins are outputs when

the corresponding Byte Enable (BE) is HIGH and SOE is LOW.

System Output Enable: enables system data bus output drivers if the corresponding Byte Enable

(BE0-7) is HIGH.

Byte Enable: is used along with SOE, to enable the System Data outputs for a particular byte. For

example, if BE1 is HIGH, the System data outputs for byte 1 (SD8-15) are enabled. The BE0-7 pins also

control the byte mux. If a particular BE is HIGH during a memory read cycle, that byte is fed back to

the memory data bus. This is used during partial word write operations and writing corrected data back

to memory.

Memory Output Enable: when LOW, enables the output buffers of the memory data bus (MD) and

CBSYN bus. It also controls the CBSYN mux. When LOW, checkbits are selected, when HIGH,

syndrome is selected.

Memory Data Input Latch Enable: on the HIGH-to-LOW transition, latches MD and CBI in MD input

latch and MD check bit latch respectively. The latches are transparent when MDILE is HIGH.

Memory Data Output Latch Enable: latches data in the MD output latch on the LOW-to-HIGH

transition of . MDOLE When MDOLE is LOW, the MD output latch is transparent.

System Data Output Latch Enable: latches data in the SD output latch and the SD checkbit latch

on the LOW-to-HIGH transition of . SDOLE The latch is transparent when SDOLE is LOW.

System Data Input Latch Enable: latches SD in the SD input latch on the HIGH-to-LOW transition.

When SDILE is HIGH, the SD input latch is transparent.

Write FIFO Select: when HIGH, the write FIFO is selected. When WBSEL is LOW, the SD input latch

is selected.

Write FIFO Enable: when LOW, allows SD data to be written to the write FIFO on the SCLK rising edge.

Write FIFO Read Enable: when LOW, allows data to be read from the the write FIFO on MCLK rising

edge.

Reset and Select pins (read and write FIFO FIFOs)

RS1 RS0 Function

0

0

Reset 16-deep FIFO or first 8-deep FIFO

0

1

Reset second 8-deep FIFO

1

0

Select 16-deep FIFO or first 8-deep FIFO

1

1

Select second 8-deep FIFO

2617 tbl 01

11.7

4

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