MCM72FB8ML7.5R Просмотр технического описания (PDF) - Motorola => Freescale

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MCM72FB8ML7.5R

256K x 72 Bit BurstRAM Multichip Module

Motorola => Freescale 

K

ADSC

STOP CLOCK WITH WRITE TIMING

ADDRESS

A1

A2

WRITE

ADV

DATA IN

D(A1)

D(A1 + 1)

VIH OR VIL FIXED (SEE NOTE)

D(A2)

HIGH–Z

DQx

ADSC

(INITIATES

BURST WRITE)

CLOCK STOP

(CONTINUE

BURST WRITE)

WAKE UP ADSC

(INITIATES BURST WRITE)

NOTE: While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the

input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control

lines held in an inactive state.

MCM72FB8ML  MCM72PB8ML

16

MOTOROLA FAST SRAM

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