MCM72FB8ML7.5R Просмотр технического описания (PDF) - Motorola => Freescale

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MCM72FB8ML7.5R

256K x 72 Bit BurstRAM Multichip Module

Motorola => Freescale 

APPLICATION INFORMATION

STOP CLOCK OPERATION

In the stop clock mode of operation, the SRAM will hold all

state and data values even though the clock is not running

(full static operation). The SRAM design allows the clock to

start with ADSP and ADSC, and stops the clock after the last

write data is latched, or the last read data is driven out.

When starting and stopping the clock, the AC clock timing

and parametrics must be strictly maintained. For example,

clock pulse width and edge rates must be guaranteed when

starting and stopping the clocks.

To achieve the lowest power operation for all three stop

clock modes, stop read, stop write, and stop deselect:

1. Force the clock to a low state.

2. Force the control signals to an inactive state (this guar-

antees any potential source of noise on the clock input

will not start an unplanned on activity).

3. Force the address inputs to a low state.

MCM72PB8ML PIPELINE STOP CLOCK WITH READ TIMING

K

ADSP

ADDRESS

A1

A2

ADV

DQx

Q(A1)

Q(A1 + 1)

Q(A2)

ADSP

(INITIATES

BURST READ)

CLOCK STOP

(CONTINUE

BURST READ)

WAKE UP ADSP

(INITIATES BURST READ)

NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (VIL).

Best results are obtained if VIL < 0.2 V.

MCM72FB8ML  MCM72PB8ML

14

MOTOROLA FAST SRAM

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