MCM69P819TQ4 Просмотр технического описания (PDF) - Motorola => Freescale

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MCM69P819TQ4

256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

Motorola => Freescale 

NON–BURST SYNCHRONOUS OPERATION

Although this BurstRAM has been designed for PowerPC–

based and other high end MPU–based systems, these

SRAMs can be used in other high speed L2 cache or

memory applications that do not require the burst address

feature. Most L2 caches designed with a synchronous inter-

face can make use of the MCM69P819. The burst counter

feature of the BurstRAM can be disabled, and the SRAM can

be configured to act upon a continuous stream of addresses.

See Figure 6.

CONTROL PIN TIE VALUES EXAMPLE (H ≥ VIH, L ≤ VIL)

Non–Burst ADSP ADSC ADV SE1 SE2 LBO

Sync Non–Burst, H

Pipelined SRAM

L

H

L

H

X

NOTE: Although X is specified in the table as a don’t care, the pin

must be tied either high or low.

K

ADDR

A

B

C

D

SE3

E

F

G

H

W

G

DQ

Q(A)

Q(B)

Q(C)

Q(D)

D(E)

D(F)

D(G)

D(H)

READS

WRITES

Figure 6. Example Configuration as Non–Burst Synchronous SRAM

ORDERING INFORMATION

(Order by Full Part Number)

Motorola Memory Prefix

Part Number

MCM

69P819

XX X

X

Blank = Trays, R = Tape and Reel

Speed (3.5 = 3.5 ns, 3.8 = 3.8 ns, 4 = 4 ns)

Package (ZP = PBGA, TQ = TQFP)

Full Part Numbers — MCM69P819ZP3.5

MCM69P819ZP3.5R

MCM69P819ZP3.8

MCM69P819ZP3.8R

MCM69P819ZP4

MCM69P819ZP4R

MCM69P819TQ4

MCM69P819TQ4R

MOTOROLA FAST SRAM

MCM69P819

17

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