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MCM6709RJ6 Datasheet PDF : 8 Pages
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CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Max
Unit
Address Input Capacitance
Control Pin Input Capacitance (E, G, W)
Input/Output Capacitance
Cin
Cin
CI/O
5
pF
6
pF
6
pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1A
READ CYCLES 1 AND 2 (See Notes 1 and 2)
MCM6709R–6
MCM6709R–7
MCM6709R–8
Parameter
Symbol
Min
Max
Min
Max
Min
Max Unit Notes
Read Cycle Time
tAVAV
6
—
7
—
8
—
ns
3
Address Access Time
tAVQV
—
6
—
7
—
8
ns
Chip Enable Access Time
tELQV
—
6
—
7
—
8
ns
Output Enable Access Time
tGLQV
—
4
—
4
—
4
ns
Output Hold from Address Change
tAXQX
3
—
3
—
3
—
ns
Chip Enable Low to Output Active
tELQX
3
—
3
—
3
—
ns 4, 5, 6
Output Enable Low to Output Active
tGLQX
0
—
0
—
0
—
ns 4, 5, 6
Chip Enable High to Output High–Z
tEHQZ
0
3
0
3.5
0
4
ns 4, 5, 6
Output Enable High to Output High–Z
tGHQZ
0
3
0
3.5
0
4
ns 4, 5, 6
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given
device and from device to device.
5. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
OUTPUT
AC TEST LOADS
Z0 = 50 Ω
RL = 50 Ω
VL = 1.5 V
OUTPUT
255 Ω
+5 V
480 Ω
5 pF
Figure 1A
Figure 1B
TIMING LIMITS
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never pro-
vides data later than that time.
MOTOROLA FAST SRAM
MCM6709R
3
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