MAX8550(2004) Просмотр технического описания (PDF) - Maxim Integrated

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MAX8550
(Rev.:2004)

Integrated DDR Power-Supply Solutions for Desktops, Notebooks, and Graphic Cards

Maxim Integrated 

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

Pin Description (continued)

PIN

NAME

FUNCTION

11

PGND2 Power Ground for VTT and VTTR. Connect PGND2 externally to the underside of the exposed pad.

12

VTT

Termination Power-Supply Output. Connect VTT to VTTS to regulate to VREFIN / 2.

13

VTTI

Power-Supply Input Voltage for VTT and VTTR. Normally connected to the output of the buck regulator

for DDR application.

14

REFIN

External Reference Input. This is used to regulate the VTT and VTTR outputs to VREFIN / 2.

Feedback Input for Buck Output. Connect to AVDD for a +1.8V fixed output or to GND for a +2.5V fixed

15

FB

output. For an adjustable output (0.7V to 5.5V), connect FB to a resistive divider from the output

voltage. FB regulates to +0.7V.

Output-Voltage Sense Connection. Connect to the positive terminal of the buck output filter capacitor.

OUT senses the output voltage to determine the on-time for the high-side switching MOSFET (Q1 in the

16

OUT

Typical Applications Circuit). OUT also serves as the buck output’s feedback input in fixed-output

modes. When discharge mode is enabled by OVP/UVP, the output capacitor is discharged through an

internal 10Ω resistor connected between OUT and GND.

17

VIN

Input-Voltage Sense Connection. Connect to input power source. VIN is used only to set the PWM’s on-

time one-shot timer. IN voltage range is from 2V to 28V.

18

DH

High-Side Gate-Driver Output. Swings from LX to BST. DH is low when in shutdown or UVLO.

19

LX

External Inductor Connection. Connect LX to the input side of the inductor. LX is used for both current

limit and the return supply of the DH driver.

20

BST

Boost Flying-Capacitor Connection. Connect to an external capacitor and diode according to the

Typical Applications Circuit (Figure 8). See the Boost-Supply Diode and Capacitor Selection section.

21

DL

Synchronous-Rectifier Gate-Driver Output. Swings from PGND to VDD.

22

VDD

Supply Input for the DL Gate Drive. Connect to the +4.5V to +5.5V system supply voltage. Bypass to

PGND1 with a 1µF (min) ceramic capacitor.

23

PGND1 Power Ground for Buck Controller. Connect PGND1 externally to the underside of the exposed pad.

24

GND

Analog Ground for Both Buck and LDO. Connect GND externally to the underside of the exposed pad.

SKIP

Pulse-Skipping Control Input. Connect to AVDD for low-noise, forced-PWM mode. Connect to GND to

(MAX8550) enable pulse-skipping operation.

25

TP1

(MAX8551)

In the MAX8551, this pin is a test pin and must be connected to GND (pin 24).

26

AVDD

Analog Supply Input for Both Buck and LDO. Connect to the +4.5V to +5.5V system supply voltage

with a series 10Ω resistor. Bypass to GND with a 1µF or greater ceramic capacitor.

27

SHDNA

Shutdown Control Input A. Use to control buck output. A rising edge on SHDNA clears the overvoltage

and undervoltage-protection fault latches (see Tables 2 and 3). Connect to AVDD for normal operation.

28

SHDNB

Shutdown Control Input B. Use to control VTT and VTTR outputs. Both VTTR and VTT are high

impedence in shutdown (see Table 2).

10 ______________________________________________________________________________________

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