MAX509ACAP Просмотр технического описания (PDF) - Maxim Integrated
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MAX509ACAP Datasheet PDF : 20 Pages
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Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±10%, VSS = 0V to -5.5V, VREF = 4V, AGND = DGND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX,
unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER SUPPLIES
Positive Supply Voltage
Negative Supply Voltage
VDD
For specified performance
VSS
For specified performance
4.5
5.5
V
-5.5
0
V
Positive Supply Current
IDD
Outputs unloaded, all
MAX5_ _C/E
digital inputs = 0V or VDD MAX5_ _M
5
10
mA
5
12
Negative Supply Current
VSS = -5V ±10%, outputs MAX5_ _C/E
ISS
unloaded, all digital
inputs = 0V or VDD
MAX5_ _M
5
10
mA
5
12
Note 1: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.
Note 2: Input capacitance is code dependent. The highest input capacitance occurs at code = 00 hex.
Note 3: VREF = 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the
code of all other DACs to 00 hex.
Note 4: VREF = 4Vp-p, 10kHz. DAC code = 00 hex.
Note 5: Guaranteed by design.
Note 6: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.
TIMING CHARACTERISTICS
(VDD = +5V ±10%, VSS = 0V to -5V, VREF = 4V, AGND = DGND = 0V, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
LDAC Pulse Width Low
tLDW
MAX5_ _C/E
MAX5_ _M
40
20
50
25
CS Rise to LDAC Fall Setup Time
CLR Pulse Width Low
tCLL
tCLW
(Notes 7, 8)
MAX5_ _C/E
MAX5_ _M
0
40
20
50
25
SERIAL INTERFACE TIMING
CS Fall to SCLK Setup Time
MAX5_ _C/E
tCSS
MAX5_ _M
40
50
SCLK Fall to CS Rise Hold Time
tCSH2
0
SCLK Rise to CS Rise Hold Time
tCSH1
(Note 9)
40
SCLK Fall to CS Fall Hold Time
tCSH0
(Note 7)
0
MAX5_ _C/E
40
DIN to SCLK Rise Setup Time
tDS
MAX5_ _M
50
DIN to SCLK Rise Hold Time
SCLK Clock Frequency
tDH
fCLK
MAX5_ _C/E
MAX5_ _M
0
20
20
MAX5_ _C/E
40
SCLK Pulse Width High
tCH
MAX5_ _M
50
MAX5_ _C/E
40
SCLK Pulse Width Low
tCL
MAX5_ _M
50
MAX5_ _C/E
10
SCLK to DOUT Valid
tDO
MAX5_ _M
10
Note 7: Guaranteed by design.
Note 8: If LDAC is activated prior to CS's rising edge, it must stay low for tLDW or longer after CS goes high.
Note 9: Minimum delay from 12th clock cycle to CS rise.
MAX UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
12.5
MHz
10
ns
ns
100
ns
100
4 _______________________________________________________________________________________
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