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M6759

8-bit MTP Micro-controller

Unspecified 

--Proprietary, Confidential, Preliminary--

Acer Laboratories Inc.

M6759: 8 bit MTP Micro-controller

3.4 Idle Mode

In Idle mode, CPU put itself into sleep while all the on-chip

peripherals remain active. The instruction that sets

PCON.0 is the last instruction executed in the normal

operating mode before Idle mode is activated. The

content of RAM and special functions register remain

unchanged, and the status of CPU (includes Stack Point,

Program Counter, Program Status Word and

Accumulator) is preserved in this mode.

There are two ways to terminate Idle mode:

• Activation of any enabled interrupt will cause IDLE

(PCON.0) to be cleared by hardware terminating Idle

mode. The interrupt will be serviced, and returned by

instruction RETI. The next instruction to be executed

is the one which follows the instruction that wrote a

logic

1

to

PCON.0.

The flag bits GF0 (PCON.2) and GF3 (PCON.6) can

be used to determine whether the interrupt was

received during normal execution or during the Idle

mode. When Idle mode is terminated by an interrupt,

the service routine can examine the status of the flag

bits.

• The second way of terminating the Idle mode is with

an external hardware reset.

3.5 PowerDown Mode

Setting PCON.1 (PD) can force CPU enter Power Down

mode. In this mode, on-chip oscillator is stopped to save

most of power. All functions are stopped due to the clock

frozen, but the contents of RAM and special functions

register are held.

To terminate Power Down mode, the only way is hardware

reset. Reset redefines the SFRs but does not change the

on-chip RAM. The reset should not be activated before

VCC is restored to its normal operating level and must be

held active long enough to allow the oscillator to restart

stably.

3.6 Reset

The RST is the reset input, which is the input to a Schmitt

Trigger. A reset is accomplished by holding the RST pin

high for at least four oscillator periods while the oscillator

is running. The CPU responds by generating an internal

reset, with the timing shown in Reset Timing.

The external reset signal is synchronous to the internal

clock. The port pins will maintain high by internal pullups

for 205 oscillator periods after RST pin goes low. While

the RST pin is high, ALE and /PSEN are weakly pulled

high. After RST is pulled low, it will take about 205

oscillator periods for ALE and PSEN to start clocking. For

this reason, other devices can not be synchronized to the

internal timings of the m6759. Driving the ALE and /PSEN

pins to 0 while reset is active could cause the device to go

into an indeterminate state.

The internal reset algorithm writes 0s to all the SFRs

except the port latches, the Stack Pointer, and SBUF. The

port latches are initialized to FFH, the Stack Pointer to

07H, and SBUF is indeterminate. The internal RAM is not

affected by reset. On power up the RAM content is

indeterminate.

3.7 Interrupt Processing

When an enabled interrupt occurs, the CPU vectors to the

address of the interrupt service routine (ISR) associated

with that interrupt, as listed in Table 11. The CPU

executes the ISR to completion unless another interrupt of

higher priority occurs. Each ISR ends with a RETI (return

from interrupt) instruction. After executing the RETI, the

CPU returns to the next instruction that would have been

executed if the interrupt had not occurred.

An ISR can only be interrupted by a higher priority

interrupt. That is, an ISR for a low-priority level interrupt

can only be interrupted by high-priority level interrupt. An

ISR for a high-priority level cannot be interrupted by any

other interrupt.

M6759 always completes the instruction in progress

before servicing an interrupt. If the instruction in progress

is RETI, or a write access to any of the IP or IE SFRs,

M6759 completes one additional instruction before

servicing the interrupt.

3.8 Interrupt Masking

The EA bit in the IE SFR (IE.7) is a global enable for all

interrupts. When EA=1, each interrupt is enabled/masked

by its individual enable bit. When EA=0, all interrupts are

masked.

Page 8

Ver.1.01, Doc. No.: 6759DS02.doc

Acer Labs: 11F, no.45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030

Homepage: www.ali.com.tw

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