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M25PE40

4 Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout

STMicroelectronics 

M25PE40

SPI MODES

These devices can be driven by a microcontroller

with its SPI peripheral running in either of the two

following modes:

– CPOL=0, CPHA=0

– CPOL=1, CPHA=1

For these two modes, input data is latched in on

the rising edge of Serial Clock (C), and output data

is available from the falling edge of Serial Clock

(C).

The difference between the two modes, as shown

in Figure 5., is the clock polarity when the bus

master is in Stand-by mode and not transferring

data:

– C remains at 0 for (CPOL=0, CPHA=0)

– C remains at 1 for (CPOL=1, CPHA=1)

Figure 4. Bus Master and Memory Devices on the SPI Bus

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

Bus Master

(ST6, ST7, ST9,

ST10, Others)

SDO

SDI

SCK

CS3 CS2 CS1

CQD

SPI Memory

Device

S

TSL RP

CQD

SPI Memory

Device

S

TSL RP

CQD

SPI Memory

Device

S

TSL RP

Note: The Top Sector Lock (TSL) signal should be driven, High or Low as appropriate.

Figure 5. SPI Modes Supported

CPOL CPHA

0

0

C

1

1

C

D

Q

MSB

MSB

AI10741B

AI01438B

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