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M25PE40

4 Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout

STMicroelectronics 

M25PE40

SIGNAL DESCRIPTION

Serial Data Output (Q). This output signal is

used to transfer data serially out of the device.

Data is shifted out on the falling edge of Serial

Clock (C).

Serial Data Input (D). This input signal is used to

transfer data serially into the device. It receives in-

structions, addresses, and the data to be pro-

grammed. Values are latched on the rising edge of

Serial Clock (C).

Serial Clock (C). This input signal provides the

timing of the serial interface. Instructions, address-

es, or data present at Serial Data Input (D) are

latched on the rising edge of Serial Clock (C). Data

on Serial Data Output (Q) changes after the falling

edge of Serial Clock (C).

Chip Select (S). When this input signal is High,

the device is deselected and Serial Data Output

(Q) is at high impedance. Unless an internal Read,

Program, Erase or Write cycle is in progress, the

device will be in the Standby Power mode (this is

not the Deep Power-down mode). Driving Chip

Select (S) Low selects the device, placing it in the

Active Power mode.

After Power-up, a falling edge on Chip Select (S)

is required prior to the start of any instruction.

Reset (Reset). The Reset (Reset) input provides

a hardware reset for the memory.

When Reset (Reset) is driven High, the memory is

in the normal operating mode. When Reset (Re-

set) is driven Low, the memory will enter the Reset

mode. In this mode, the output is high impedance.

Driving Reset (Reset) Low while an internal oper-

ation is in progress will affect this operation (write,

program or erase cycle) and data may be lost.

Top Sector Lock (TSL). This input signal puts

the device in the Hardware Protected mode, when

Top Sector Lock (TSL) is connected to VSS, caus-

ing the top 256 pages (upper addresses) of the

memory to become read-only (protected from

write, program and erase operations).

When Top Sector Lock (TSL) is connected to VCC,

the top 256 pages of memory behave like the other

pages of memory.

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