LTC2264IUJ-12-TRPBF Просмотр технического описания (PDF) - Linear Technology

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LTC2264IUJ-12-TRPBF

12-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs

Linear Technology 

LTC2265-12/

LTC2264-12/LTC2263-12

TIMING DIAGRAMS

2-Lane Output Mode, 16-Bit Serialization

ANALOG

INPUT

ENC–

ENC+

DCO–

tAP

N

tENCH

tENCL

N+1

tSER

DCO+

FR–

tFRAME

tDATA

tSER

FR+

tPD

tSER

OUT#A–

OUT#A+

D3 D1 DX* 0 D11 D9 D7 D5 D3 D1 DX* 0 D11 D9 D7

OUT#B–

OUT#B+

D2 D0 DY* 0 D10 D8 D6 D4 D2 D0 DY* 0 D10 D8 D6

SAMPLE N-6

SAMPLE N-5

SAMPLE N-4

226512 TD01

*DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT

VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO

LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.

2-Lane Output Mode, 14-Bit Serialization

ANALOG

INPUT

ENC–

ENC+

DCO–

tAP

N

tENCH

tENCL

N+1

tSER

N+2

DCO+

FR–

tFRAME

tDATA

tSER

FR+

tPD

tSER

OUT#A–

OUT#A+

D5 D3 D1 DX* D11 D9 D7 D5 D3 D1 DX* D11 D9 D7 D5 D3 D1 DX* D11 D9 D7

OUT#B–

OUT#B+

D4 D2 D0 DY* D10 D8 D6 D4 D2 D0 DY* D10 D8 D6 D4 D2 D0 DY* D10 D8 D6

226512 TD02

SAMPLE N-6

SAMPLE N-5

SAMPLE N-4

SAMPLE N-3

NOTE THAT IN THIS MODE, FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC–

*DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT

VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO

LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.

8

22654312f

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