LTC2264IUJ-12-TRPBF Просмотр технического описания (PDF) - Linear Technology
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LTC2264IUJ-12-TRPBF Datasheet PDF : 32 Pages
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LTC2265-12/
LTC2264-12/LTC2263-12
TIMING DIAGRAMS
1-Lane Output Mode, 14-Bit Serialization
ANALOG
INPUT
ENC–
tAP
N
tENCH
tENCL
N+1
ENC+
DCO–
tSER
DCO+
FR–
tFRAME
tDATA
tSER
FR+
tPD
tSER
OUT#A–
OUT#A+
D1 D0 DX* DY* D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DX* DY* D11 D10 D9 D8
226512 TD05
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
OUT#B+, OUT#B– ARE DISABLED
*DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
1-Lane Output Mode, 12-Bit Serialization
ANALOG
INPUT
ENC–
tAP
N
tENCH
tENCL
N+1
ENC+
DCO–
tSER
DCO+
FR–
tFRAME
tDATA
tSER
FR+
tPD
tSER
OUTA–
OUTA+
D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9
226512 TD06
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
OUTB+, OUTB– ARE DISABLED
SPI Port Timing (Readback Mode)
tS
tDS
tDH
tSCK
tH
CS
SCK
tDO
SDI
R/W
A6
A5
A4
A3
A2
A1
A0
XX
XX
XX
XX
XX
XX
XX
XX
SDO
HIGH IMPEDANCE
D7
D6
D5
D4
D3
D2
D1
D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDO
HIGH IMPEDANCE
10
226512 TD07
22654312f
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