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LTC1098LAC Просмотр технического описания (PDF) - Linear Technology

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LTC1098LAC Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
LTC1096L/LTC1098L
PI FU CTIO S
CH1 (Pin 3): Analog Input. This input must be free of noise
with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
DIN (Pin 5): Digital Data Input. The multiplexer address is
shifted into this pin.
DOUT (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the serial
data transfer.
VCC (VREF) (Pin 8): Power Supply Voltage. This pin pro-
vides power and defines the span of the A/D converter. It
must be free of noise and ripple by bypassing directly to
the analog ground plane
TEST CIRCUITS
Load Circuit for tdDO, tr and tf
1.4V
DOUT
3k
100pF
TEST POINT
LTC1096/98 • TC01
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
DOUT
tr
VOH
VOL
tf
LTC1096/98 • TC02
Load Circuit for tdis and ten
TEST POINT
DOUT
3k
100pF
VCC tdis WAVEFORM 2, ten
tdis WAVEFORM 1
LTC1096/98 • TC03
Voltage Waveforms for tdis
CS
VIH
DOUT
WAVEFORM 1
(SEE NOTE 1)
90%
tdis
DOUT
WAVEFORM 2
(SEE NOTE 2)
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
LTC1096/98 • TC04
Voltage Waveforms for DOUT Delay Time, tdDO
CLK
DOUT
VIL
tdDO
VOH
VOL
LTC1096/98 • TC05
5

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