datasheetbank_Logo
Технический паспорт Поисковая и бесплатно техническое описание Скачать

LIS331DL Просмотр технического описания (PDF) - STMicroelectronics

Номер в каталоге
Компоненты Описание
Список матч
LIS331DL Datasheet PDF : 42 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
LIS331DL
Mechanical and electrical specifications
2.3.2
I2C - Inter IC control interface
Subject to general operating conditions for Vdd and top.
Table 6.
Symbol
I2C slave timing values
Parameter
I2C Standard mode(1)
Min
Max
I2C Fast mode (1)
Min
Max
Unit
f(SCL)
SCL clock frequency
0
100
0
400
KHz
tw(SCLL)
SCL clock low time
4.7
tw(SCLH) SCL clock high time
4.0
1.3
µs
0.6
tsu(SDA)
SDA setup time
250
100
ns
th(SDA)
SDA data hold time
0(2)
3.45
0(2)
0.9
µs
tr(SDA) tr(SCL) SDA and SCL rise time
tf(SDA) tf(SCL) SDA and SCL fall time
1000
20 + 0.1Cb (3)
300
ns
300
20 + 0.1Cb (3)
300
th(ST)
START condition hold time
4
0.6
tsu(SR)
Repeated START condition
setup time
4.7
tsu(SP)
STOP condition setup time
4
0.6
µs
0.6
tw(SP:SR)
Bus free time between STOP
and START condition
4.7
1.3
1. Data based on standard I2C protocol requirement, not tested in production
2. A device must internally provide an hold time of at least 300ns for the SDA signal (referred to VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL
3. Cb = total capacitance of one bus line, in pF
Figure 4. I2C slave timing diagram (4)
START
REPEATED
START
SDA
tsu(SR)
tw(SP:SR)
START
tf(SDA)
SCL
tr(SDA)
tsu(SDA)
th(SDA)
tsu(SP)
STOP
th(ST) tw(SCLL)
tw(SCLH)
tr(SCL)
tf(SCL)
4. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports
13/42

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]