LH28F320BJE-PTTL90 Просмотр технического описания (PDF) - Sharp Electronics

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LH28F320BJE-PTTL90

Flash Memory 32M (2M × 16/4M × 8)

Sharp Electronics 

SHARP

LHF32JO2

28

5.6 Power-Up/Down Protection

The device is designed to offer protection against

accidental block erase, full chip erase, word/byte write or

lock-bit configuration during power transitions. Upon

power-up, the device is indifferent as to which power

Supply (Vccw or V,,) powers-up first. Internal circuitry

resets the CUI to read array mode at power-up.

A system designer must guard against spurious writes for

V,, voltages above VLKO when Vccw is active. Since

both WE# and CE# must be low for a command write,

driving either to V,, will inhibit writes. The CUPS two-

step command sequence architecture prov.ides added level

Df protection against data alteration.

c

In-system block lock and unlock capability prevents

inadvertent data alteration. The device is disabled while

RP#=V, regardless of its control inputs state.’

5.7 Power Dissipation

When designing portable systems. designers must consider

lattery power consumption not only during device

operation, but also for data retention during system idle

ime. Flash memory’s nonvolatility increases usable

Iattery life because data is retained when system power is

.emoved.

5.8 Data Protection Method

Noises having a level exceeding the limit specified in the

specification may be generated under specific operating

conditions on some systems. Such noises, when induced

onto WE# signal or power supply. may be interpreted as

false commands, causing undesired memory updating. To

protect the data stored in the flash memory against

unwanted overwriting. systems operating with the flash

memory should have the following write protect designs.

as appropriate:

1) Protecting data in specific block

When a lock bit is set. the corresponding block (includes

the 2 boot blocks) is protected against overwriting. By

setting a WP# to low. only the 2 boot blocks can be

protected against overwriting. By using this feature, the

flash memory space can be divided into the program

section (locked section) and data section (unlocked

section). The permanent lock bit can be used to prevent

false block bit setting. For further information on

setting/resetting lock-bit. refer to the specification. (See

chapter 4.10 and 4.11.)

2) Data protection through Vccw

When the level of V,-,, is lower than VCC,vrK (lockout

voltage), write operation on the flash memory is disabled.

All blocks are locked and the data in the blocks are

completely write protected. For the lockout voltage. refer

to the specification. (See chapter 6.2.3.)

3) Data protection through RP#

When the RP# is kept low during read mode. the flash

memory will be deep-power-down mode. then write

protecting all blocks. When the RF% is kept low during

power up and power down sequence such as voltage

transition. write operation on the flash memory is disabled.

write protecting all blocks. For the details of RP# control.

refer to the specification. (See chapter 5.6 and 6.2.7.)

Rev. 1.25

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