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LH28F040SUT-Z4

4M (512K × 8) Flash Memory

Sharp Electronics 

LH28F040SUTD-Z4

4M (512K × 8) Flash Memory

LH28F040SUTD-Z4 Performance Enhancement Command Bus Definitions

Following is the commands to be applied to each bank.

COMMAND

FIRST BUS CYCLE SECOND BUS CYCLE

THIRD BUS CYCLE

OPER. ADD. DATA OPER. ADD. DATA OPER. ADD. DATA

NOTE

Protect Set/Confirm

Write X 57H Write 0FFH D0H

1, 2, 6

Protect Reset/Confirm

Write X 47H Write 0FFH D0H

3, 6

Lock Block/Confirm

Write X 77H Write BA

D0H

1, 2, 4

Bank Erase All Unlocked Blocks Write X A7H Write X

D0H

1, 2

Two-Byte Write

Write X FBH Write A10 WD (L, H) Write WA WD (H, L) 1, 2, 5

ADDRESS

BA = Block Address

WA = Write Address

X = Don’t Care

DATA

AD = Array Data

WD (L, H) = Write Data (Low, High)

WD (H, L) = Write Data (High, Low)

NOTES:

1. After initial device power-up, or reset is completed, the block lock status bit default to the locked state independent of the data in the

corresponding lock bits. In order to upload the lock bit status, it requires to write Protect Set/Confirm command.

2. To reflect the actual lock-bit status, the Protect Set/Confirm command must be written after Lock Block/Confirm command.

3. When Protect Reset/Confirm command is written, all blocks can be written and erased regardless of the state of the lock-bits.

4. The Lock Block/Confirm command must be written after Protect Reset/Confirm command was written.

5. A0 is automatically complemented to load second byte of data A0 value determines which WD is supplied first: A0 = 0 looks at the

WDL, A0 = 1 looks at the WDH.

6. Second bus cycle address of Protect Set/Confirm and Protect Reset/Confirm command is 0FFH. Specifically A9 - A8 = 0, A7 - A0 = 1,

others are don’t care.

Compatible Status Register

Following is the commands to be applied to each bank.

WSMS

ESS

ES

DWS

VPPS

R

R

R

7

6

5

4

3

2

1

0

CSR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready

2 = Busy

CSR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended

0 = Erase in Progress/Completed

CSR.5 = ERASE STATUS (ES)

1 = Error in Block Erasure

0 = Successful Block Erase

CSR.4 = DATA-WRITE STATUS (DWS)

1 = Error in Data Write

0 = Data Write Successful

CSR.3 = VPP STATUS (VPPS)

1 = VPP Low Detect, Operation Abort

0 = VPP OK

NOTES:

1. RY »/BY » output or WSMS bit must be checked to determine

completion of an operation (Erase Suspend, Erase or Data

Write) before the appropriate Status bit (ESS, ES or DWS)

is checked for success.

2. If DWS and ES are set to ‘1’ during an erase attempt, an

improper command sequence was entered. Clear the CSR

and attempt the operation again.

3. The VPPS bit, unlike an A/D converter, does not provide

continuous indication of VPP level. The WSM interrogates

VPP’s level only after the Data-Write or Erase command

sequences have been entered, and informs the system if

VPP has not been switched on. VPPS is not guaranteed to

report accurate feedback between VPPL and VPPH.

4. CSR.2 - CSR.0 = Reserved for further enhancements.

These bits are reserved for future use and should be

masked out when polling the CSR.

8

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