ISP1563 Просмотр технического описания (PDF) - Philips Electronics
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ISP1563 Datasheet PDF : 107 Pages
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Philips Semiconductors
ISP1563
HS USB PCI Host Controller
8.2.1.6 Class Code register
Class Code is a 24-bit read-only register used to identify the generic function of the
device, and in some cases, a specific register-level programming interface. Table 11
shows the bit allocation of the register.
The Class Code register is divided into three byte-size fields. The upper byte is a base
class code that broadly classifies the type of function the device performs. The middle
byte is a sub-class code that identifies more specifically the function of the device. The
lower byte identifies a specific register-level programming interface, if any, so that
device-independent software can interact with the device.
Table 11: Class Code register (address 09h) bit allocation
Bit
23
22
21
20
19
18
17
16
Symbol
BCC[7:0]
Reset
0Ch
Access
R
R
R
R
R
R
R
R
Bit
15
14
13
12
11
10
9
8
Symbol
SCC[7:0]
Reset
03h
Access
R
R
R
R
R
R
R
R
Bit
7
6
5
4
3
2
1
0
Symbol
RLPI[7:0]
Reset
X0h [1]
Access
R
R
R
R
R
R
R
R
[1] X is 1h for OHCI1 and OHCI2; X is 2h for EHCI.
Table 12:
Bit
23 to 16
15 to 8
7 to 0
Class Code register (address 09h) bit description
Symbol
Description
BCC[7:0]
Base Class Code: 0Ch is the base class code assigned to this byte. It
implies a serial bus controller.
SCC[7:0]
Sub-Class Code: 03h is the sub-class code assigned to this byte. It
implies the USB Host Controller.
RLPI[7:0]
Register-Level Programming Interface: 10h is the programming
interface code assigned to OHCI, which is USB 1.1 specification
compliant. 20h is the programming interface code assigned to EHCI,
which is USB 2.0 specification compliant.
8.2.1.7 CacheLine Size register
The CacheLine Size register is a read and write single-byte register that specifies the
system CacheLine size in units of DWords. This register must be implemented by master
devices that can generate the Memory Write and Invalidate command. The value in this
register is also used by master devices to determine whether to use Read, Read Line or
Read Multiple commands to access the memory.
Slave devices that want to allow memory bursting using a CacheLine-wrap addressing
mode must implement this register to know when a burst sequence wraps to the
beginning of the CacheLine.
9397 750 14224
Product data sheet
Rev. 01 — 14 July 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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