ISP1563 Просмотр технического описания (PDF) - Philips Electronics

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ISP1563

Hi-Speed Universal Serial Bus PCI Host Controller

Philips Electronics 

Philips Semiconductors

ISP1563

HS USB PCI Host Controller

Table 20: CP - Capabilities Pointer register (address 34h) bit description

Legend: * reset value

Bit Symbol Access Value Description

7 to 0 CP[7:0] R

DCh*

Capabilities Pointer: EHCI efficiently manages power

using this register. This Power Management register is

allocated at offset DCh. Only one Host Controller is

needed to manage power in the ISP1563.

8.2.1.14 Interrupt Line register

This is a 1 B register used to communicate interrupt line routing information. This register

must be implemented by any device or device function that uses an interrupt pin. The

interrupt allocation is done by the BIOS. The Power On Self Test (POST) software needs

to write the routing information to this register because it initializes and configures the

system. The value in this register specifies which input of the system interrupt controller(s)

the interrupt pin of the device is connected. This value is used by device drivers and

operating systems to determine priority and vector information. Values in this register are

system architecture specific. The bit description of the register is given in Table 21.

Table 21: IL - Interrupt Line register (address 3Ch) bit description

Legend: * reset value

Bit Symbol Access Value

Description

7 to 0 IL[7:0] R/W

00h*

Interrupt Line: Indicates which IRQ is used to report

interrupt from the ISP1563.

8.2.1.15 Interrupt Pin register

This 1 B register is use to specify which interrupt pin the device or device function uses.

A value of 1h corresponds to INTA#, 2h corresponds to INTB#, 3h corresponds to INTC#,

and 4h corresponds to INTD#. Devices or functions that do not use interrupt pin must set

this register to logic 0. The bit description is given in Table 22.

Table 22: IP - Interrupt Pin register (address 3Dh) bit description

Legend: * reset value

Bit Symbol Access Value

Description

7 to 0 IP[7:0] R

01h*

Interrupt Pin: INTA# is the default interrupt pin used

by the ISP1563.

8.2.1.16 Min_Gnt and Max_Lat registers

The Minimum Grant (Min_Gnt) and Maximum Latency (Max_Lat) registers are used to

specify the desired settings of the device for latency timer values. For both registers, the

value specifies a period of time in units of 250 ns. Logic 0 indicates that the device has no

major requirements for setting latency timers. The Min_Gnt register bit description is given

in Table 23.

Table 23: Min_Gnt - Minimum Grant register (address 3Eh) bit description

Legend: * reset value

Bit Symbol Access Value Description

7 to 0 MIN_GNT R

[7:0]

0Xh* [1] Min_Gnt: It is used to specify how long a burst period

the device needs, assuming a clock rate of 33 MHz.

[1] X is 1h for OHCI1 and OHCI2; X is 2h for EHCI.

9397 750 14224

Product data sheet

Rev. 01 — 14 July 2005

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

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