ISL97649B Просмотр технического описания (PDF) - Intersil
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ISL97649B Datasheet PDF : 19 Pages
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ISL97649B
Electrical Specifications VIN = ENABLE = 3.3V, AVDD = 8V, VON = 24V, VOFF = -6V. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
(Note 7)
MAX
(Note 6)
UNITS
DIGITAL CONTROLLED POTENTIOMETER
SETVR
SETDNL
SET Voltage Resolution (Note 12)
SET Differential Nonlinearity (Notes 8, 9, TA = +25°C
14)
8
Bits
-
-
±1
LSB
SETZSE SET Zero-Scale Error (Note 10,14)
SETFSE SET Full-Scale Error (Note 11,14)
IRSET
RSET Current
AVDD to SET AVDD to SET Voltage Attenuation
TA = +25°C
TA = +25°C
-
-
±2
LSB
-
-
±8
LSB
-
100
µA
-
1:20
-
V/V
FAULT DETECTION THRESHOLD
VUVLO Undervoltage Lock-out Threshold
OVPAVDD Boost Overvoltage Protection Off
Threshold to Shut Down IC (Note 13)
PVIN rising
PVIN falling
2.25
2.33
2.41
V
2.125
2.20
2.27
V
15.0
15.5
16.0
V
TOFF
Thermal Shut-Down all channels
POWER SEQUENCE TIMING
Temperature rising
153
°C
ISS
Boost Soft-start Current
3
5.5
8
µA
Serial Interface Specifications For SCL and SDA, unless otherwise noted. Boldface limits apply over the operating temperature
range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 14)
TYP
MAX
(Note 7) (Note 14) UNITS
fSCL SCL Frequency (Note 6)
tiN
Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is
and SCL Inputs (Note 6)
suppressed.
400
kHz
50
ns
tAA SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of VIN, until
SDA exits the 30% to 70% of VIN window.
tBUF Time the Bus Must be Free Before the SDA crossing 70% of VCC during a STOP
480
Start of a New Transmission
condition, to SDA crossing 70% of VIN during
the following START condition.
480
ns
ns
tLOW Clock LOW Time
Measured at 30% of VIN crossing.
480
ns
tHIGH Clock HIGH Time
Measured at 70% of VIN crossing.
400
ns
tSU:STA START Condition Set-up Time
SCL rising edge to SDA falling edge, both
480
ns
crossing 70% of VIN.
tHD:STA START Condition Hold Time
From SDA falling edge crossing 30% of VIN to
400
ns
SCL falling edge crossing 70% of VIN.
tSU:DAT Input Data Set-up Time
From SDA exiting 30% to 70% of VIN window
40
ns
to SCL rising edge crossing 30% of VIN.
tHD:DAT Input Data Hold Time
From SCL rising edge crossing 70% of VIN to
0
ns
SDA entering 30% to 70% of VIN window.
tSU:STO STOP Condition Set-up Time
From SCL rising edge crossing 70% of VIN to
400
ns
SDA rising edge crossing 30% of VIN.
tHD:STO STOP Condition Hold Time for Read, or From SDA rising edge to SCL falling edge,
400
ns
Volatile Only Write
both crossing 70% of VIN.
CSCL Capacitive on SCL
5
pF
6
FN7927.0
December 5, 2011
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