ISL97649B Просмотр технического описания (PDF) - Intersil
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ISL97649B Datasheet PDF : 19 Pages
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ISL97649B
Application Diagram
VIN
C1,2
20µF
C32
VIN
0.1µF
AVDD
C19
0.47µF
R9
10k
133k
R8 R7
83k
VCOM
VIN
EN
SS
FREQ SEQUENCER
AVDD BOOST
CONTROLLER
L1 10µH
LX
PGND
D1
C4,5,6
30µF
SW
R1
73.2k
AVDD
C7
0.1µF AVDD
FB
COMP
R2 8.06k
R12 5.5k C20 15nF
D4
Q1
VOFF
SCL
SDA
RSET
POS
AVDD
OUT
NEG
DCP
GPM
VCOM OP
VOLTAGE
DETECTOR
THERMAL PAD
VFLK
VGH
VDPM
CE
RE
VGHM
GPM_LO
VDIV
C11 C15
0.1µF 1µF
AVDD
C8
47nF
D2 C9
1µF
C17 1nF
C14 100pF
R5 100k
C18
0.47µF
R14 85k
R6 1k
C16
Z1 1µF
SW
C10
47nF
VON
D3
C12
1µF
C28
0.1µF
VGH GPM
R22 22k
R26 100k
Vin
AVDD
VGH
CD2
RESET
OPEN
R15 115k
C26 1nF
RESET
R16
10k
VLOGIC
Pin Descriptions
PIN#
1
2
3
4
5
6
7
8
9
10
11
SYMBOL
DESCRIPTION
FB AVDD boost converter feedback. Connect to the center of a voltage divider between AVDD and GND to set the AVDD voltage.
PGND Power ground
CE Gate Pulse Modulator delay control. Connect a capacitor between this pin and GND to set the delay time.
RE Gate Pulse Modulator slew control. Connect a resistor between this pin and GND to set the falling slew rate.
VGH Gate Pulse Modulator high voltage input. Place a 0.1µF decoupling capacitor close to VGH pin.
VGHM Gate Pulse Modulator output for gate drive IC.
VFLK
VDPM
Gate Pulse Modulator control input from TCON.
Gate Pulse Modulator enable. Connect a capacitor from VDPM to GND to set the delay time before GPM is enabled. A current
source charges the capacitor on VDPM.
GPM_LO Gate Pulse Modulator low voltage input. Place a 0.47µF decoupling capacitor close to GPM_LO pin.
AVDD
SCL
DCP and VCOM amplifier high voltage analog supply. Place a 0.47µF decoupling capacitor close to AVDD pin.
I2C compatible clock input
2
FN7927.0
December 5, 2011
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