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ISL97653A Просмотр технического описания (PDF) - Intersil

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ISL97653A Datasheet PDF : 18 Pages
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ISL97653A
Typical Performance Curves (Continued)
Ch1 = LXL (400ns/DIV)
Ch2 = ILXL (400ns/DIV)
Ch1 = LXL (400ns/DIV)
Ch2 = ILXL (400ns/DIV)
FIGURE 13. BOOST CURRENT LIMIT
FIGURE 14. BUCK CURRENT LIMIT
Pin Descriptions
PIN NUMBER
1
2
3, 4
5, 6
PIN NAME
DESCRIPTION
PVIN2
Logic buck supply voltage. This is also the analog supply from which the VL is generated. Needs at
least 1µF bypassing.
CB
Logic buck boot strap pin. Generate the gate drive voltage for the N-Channel MOSFET by connecting
a 1µF cap to the switching node LXL1, 2.
LXL1, LXL2 Logic buck switching node. Source of the high side internal power N-Channel MOSFET for the Buck.
PGND3, PGND4 Logic buck ground pin.
7
CM2
Buck compensation pin. An RC network is recommended. Increase R for better transient response at
the expense of stability.
8
FBL
Logic buck feedback pin. High impedance input to regulate at 1.215V.
9
VL
5.25V internal regulator output. Bypass with a 4.7µF capacitor. Ref voltage is generated from VL.
10
VREF
Reference voltage output. Bypass with a low valued capacitor for transients - recommend 220nF.
Should not be greater than 5 times CDEL capacitor to ensure correct start-up sequence.
11
FBN
Negative charge pump feedback pin. High impedance input to regulate to 0.203V.
12
SUPN
Negative charge pump supply voltage. Can be the same as or different from AVDD.
13
NOUT
Negative charge pump driver output.
14
PGND5
Charge pump ground pin.
15
C1P
Charge pump capacitor 1, positive connection.
16
C1N
Charge pump capacitor 1, negative connection.
17
C2P
Charge pump capacitor 2, positive connection.
18
C2N
Charge pump capacitor 2, negative connection.
19
SUPP
Positive charge pump supply. Can be the same as or different from AVDD.
20
FBP
Positive charge pump feedback pin. High impedance input to regulate at 1.215V
21
POUT
VON charge pump output.
22
COM
High voltage switch control output. VON slice output.
23
DRN
Lower reference voltage for VON slice output. Usually connected to AVDD.
24
CTL
Input control pin for VON slice output.
9
FN6367.3
September 7, 2010

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