ISL97653A Просмотр технического описания (PDF) - Intersil

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ISL97653A

5-Channel Integrated LCD Supply

Intersil 

ISL97653A

Pin Descriptions (Continued)

PIN NUMBER

PIN NAME

DESCRIPTION

25

CDEL

VON slice control delay input. Minimum 47nF. Recommend 220nF but is only limited by leakage in the

cap reaching µA levels.

26

EN

Chip enable (active high). Can be driven to VIN levels.

27

HVS

High-voltage stress input select pin. High selects high voltage mode.

28

RSET

Voltage set pin for HVS test. RSET connects to ground in the high voltage mode - RSET high.

29

FBB

AVDD boost feedback pin. High impedance input to regulate at 1.215V.

30

COMP

Boost compensation network pin. An RC network is recommended. Increase R for better transient

response at the expense of stability. R = 0Ω is recommended for 4.4A Boost requirements.

31

TEMP

Temperature sensor output voltage. An analog voltage from 0V to 3V for temperatures of -40°C to

+150°C.

32, 33

PGND1, PGND2 Boost ground pins.

34, 35

LX1, LX2

Boost switch output. Drain of the internal power NMOS for the Boost.

36

PROT

Gate driver of the Input protection switch. Goes low when EN is high. Can be used to modulate the

passive input inrush current as shown by R21,R22, and C30 in the “Typical Application Diagram” on

page 5.

37

AGND

Analog ground. Separate from PGND’s and star under the chip.

38

PVIN1

Logic buck supply voltage.This is also the analog supply from which the VL is generated. Needs at least

1µF bypassing.

39

LDO-FB

LDO controller feedback. High impedance input to regulate at 1.215V.

40

LDO-CTL

LDO control pin. Gate drive for the external PNP BJT.

10

FN6367.3

September 7, 2010

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