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ISL80083

2.5MHz Integrated Power Management IC with I2C Compatible Interface

Intersil 

Pin Configuration

ISL80083

ISL80083

(25 BALL CSP 2.11 x 2.13mm)

TOP VIEW

1

2

3

4

5

A

-OSCOUT

+OSCOUT

OSCGND

CLK2P3IN

CLK2P3OUT

B

CFG2

LSRX

C

CFG2_CR

LSRX_CR

D

VIN_REMOTE

OSC_EN

E

VIN_HOST

VSELECT

UART_EN

RESET

V3CLAMP

VOLDO

GNDLDO

GND

SCLK

SDAT

1VAUX

PHASE

PGND

FB

Pin Descriptions

PIN NUMBER

A1

A2

A3

A4

A5

B1

B2

B3

B4

B5

C1

C2

C3

PIN NAME

-OSCOUT

+OSCOUT

OSCGND

CLK2P3IN

CLK2P3OUT

CFG2

LSRX

UART_EN

RESET

V3CLAMP

CFG2_CR

LSRX_CR

VOLDO

DESCRIPTION

Negative terminal of the precision 33MHz oscillator differential output.

Positive terminal of the precision 33MHz oscillator differential output.

Isolated ground for the internal 33MHz oscillator.

2.3V input for the 33MHz oscillator. Connect a 220nF capacitor from CLK2P3OUT to OSCGND.

2.3V internal LDO output for the 33MHz oscillator. Connect CLK2P3IN to CLK2P3OUT along with a 220nF capacitor

for low noise performance.

This is the output of the level shifter from the CFG2_CR rail control signal shifting from 1.8V to 3V.

This is the output of the level shifter from the LSRX_CR rail control signal shifting from 1.8V to 3V.

Level shift of LSRX logic enable control. The output LSRX is in high Z state when UART_EN is pulled low. There is a

125kΩ pull-down resistor from this pin to GND.

This is a totem pole output to indicate a fault mode. The output is low if any of the fault is detected. The output is high

during normal operation.

This rail is a 3V LDO sourcing from VSELECT.

This is the input to the level shifter for the CONFIG2 rail control signal shifting from 3V to 1.8V.

This is the input to the level shifter from the LSRX rail control signal.

Output of the LDO.

2

FN7886.1

May 15, 2013

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